RTAX2000S-CG624PROTO vs RTAX2000S-CGS624V Vergleich
Detaillierter Direktvergleich von RTAX2000S-CG624PROTO von Microchip Technology und RTAX2000S-CGS624V von Microchip Technology. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Microchip Technology
RTAX2000S-CG624PROTO - 2M-Gate Rad-Tolerant FPGA CCGA-624 | Microchip
RTAX2000S-CG624PROTO ✓ AktivMicrochip Technology
RTAX2000S-CGS624V - 2M-Gate Rad-Tolerant FPGA CG624 | Microchip
RTAX2000S-CGS624V ✓ AktivSpezifikationsvergleich
| Parameter | RTAX2000S-CG624PROTO | RTAX2000S-CGS624V |
|---|---|---|
| Marke | Microchip Technology | Microchip Technology |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $0,00 | $0,00 |
| Family | RTAX-S Radiation-Tolerant FPGA | RTAX-S/SL Radiation-Tolerant FPGA |
| System Gates | 2,000,000 | — |
| Logic Cells (R-cells) | 21,504 | — |
| D-Flip-Flops (Registers) | 32,256 | — |
| Logic Architecture | CMOS antifuse (OTP), SEU-hardened | — |
| Gehäuse | CCGA-624 (ceramic column grid array, 624 balls) | CG624 ceramic column grid array |
| Montageart | Surface Mount | Surface Mount |
| Betriebstemperatur | -55C to +125C | -55C to +125C |
| Logic Family | CMOS | — |
| Configuration | Live at power-up (non-volatile antifuse) | — |
| SEU Immunity | SEU rate < 10^-10 errors/bit-day (per family datasheet) | — |
| Prototyping Variant | Yes (PROTO suffix) | — |
| Embedded Memory | Embedded SRAM blocks (FIFO / dual-port capable) | Embedded SRAM with built-in FIFO control logic |
| I/O Standards | Single-ended and differential (P/N pin pairs) | — |
| Design Software | Microsemi/Microchip Libero SoC | — |
| Versorgungsspannung | [DATA_NEEDED: core and I/O supply voltage] | — |
| Total Ionizing Dose (TID) | [DATA_NEEDED: TID rating in krad(Si)] | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance] | — |
| Maximum I/O Count (624-ball pkg) | [DATA_NEEDED: user I/O count] | — |
| Moisture Sensitivity Level | [DATA_NEEDED: MSL level] | — |
| Equivalent System Gates | — | 2000000 |
| Configurable Logic Blocks (CLBs) | — | 21504 |
| Logic Cells | — | 32256 |
| Technology | — | Digital CMOS, anti-fuse OTP |
| Core Supply Voltage (Nominal) | — | 1.5 V |
| Core Supply Voltage Range | — | 1.425 V to 1.575 V |
| Configuration Type | — | One-Time Programmable (anti-fuse), live at power-up |
| Clocking | — | Segmentable clocks |
| Routing Features | — | Chip-wide highway routing, carry logic |
| Application Domain | — | Space-flight systems |
| Max Family Density | — | 4000000 equivalent system gates (family max) |