RTAX2000S-CG624PROTO vs RTAX2000S-CGS624V Comparación

Comparación detallada lado a lado de RTAX2000S-CG624PROTO por Microchip Technology y RTAX2000S-CGS624V por Microchip Technology. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.

Microchip Technology
RTAX2000S-CG624PROTO RTAX2000S-CG624PROTO - 2M-Gate Rad-Tolerant FPGA CCGA-624 | Microchip

RTAX2000S-CG624PROTO - 2M-Gate Rad-Tolerant FPGA CCGA-624 | Microchip

RTAX2000S-CG624PROTO ✓ Activo
Microchip Technology
RTAX2000S-CGS624V RTAX2000S-CGS624V - 2M-Gate Rad-Tolerant FPGA CG624 | Microchip

RTAX2000S-CGS624V - 2M-Gate Rad-Tolerant FPGA CG624 | Microchip

RTAX2000S-CGS624V ✓ Activo

Comparación de especificaciones

Parámetro RTAX2000S-CG624PROTO RTAX2000S-CGS624V
Marca Microchip Technology Microchip Technology
Categoría FPGA & CPLD FPGA & CPLD
Estado del ciclo de vida Activo Activo
Estado del stock In Stock In Stock
Precio unitario (USD) $0,00 $0,00
Family RTAX-S Radiation-Tolerant FPGA RTAX-S/SL Radiation-Tolerant FPGA
System Gates 2,000,000 —
Logic Cells (R-cells) 21,504 —
D-Flip-Flops (Registers) 32,256 —
Logic Architecture CMOS antifuse (OTP), SEU-hardened —
Encapsulado CCGA-624 (ceramic column grid array, 624 balls) CG624 ceramic column grid array
Tipo de montaje Surface Mount Surface Mount
Temperatura de funcionamiento -55C to +125C -55C to +125C
Logic Family CMOS —
Configuration Live at power-up (non-volatile antifuse) —
SEU Immunity SEU rate < 10^-10 errors/bit-day (per family datasheet) —
Prototyping Variant Yes (PROTO suffix) —
Embedded Memory Embedded SRAM blocks (FIFO / dual-port capable) Embedded SRAM with built-in FIFO control logic
I/O Standards Single-ended and differential (P/N pin pairs) —
Design Software Microsemi/Microchip Libero SoC —
Tensión de alimentación [DATA_NEEDED: core and I/O supply voltage] —
Total Ionizing Dose (TID) [DATA_NEEDED: TID rating in krad(Si)] —
Estado RoHS [DATA_NEEDED: RoHS compliance] —
Maximum I/O Count (624-ball pkg) [DATA_NEEDED: user I/O count] —
Moisture Sensitivity Level [DATA_NEEDED: MSL level] —
Equivalent System Gates — 2000000
Configurable Logic Blocks (CLBs) — 21504
Logic Cells — 32256
Technology — Digital CMOS, anti-fuse OTP
Core Supply Voltage (Nominal) — 1.5 V
Core Supply Voltage Range — 1.425 V to 1.575 V
Configuration Type — One-Time Programmable (anti-fuse), live at power-up
Clocking — Segmentable clocks
Routing Features — Chip-wide highway routing, carry logic
Application Domain — Space-flight systems
Max Family Density — 4000000 equivalent system gates (family max)

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