SN75LVDS84ADGGR vs SN75LVDS84ADGG Vergleich
Detaillierter Direktvergleich von SN75LVDS84ADGGR von Texas Instruments und SN75LVDS84ADGG von Texas Instruments. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Texas Instruments
SN75LVDS84ADGGR - 21:3 FlatLink LVDS Transmitter 48-TSSOP | TI
SN75LVDS84ADGGR ✓ AktivTexas Instruments
SN75LVDS84ADGG - FlatLink 21:3 LVDS Transmitter | Texas Instruments
SN75LVDS84ADGG ✓ AktivSpezifikationsvergleich
| Parameter | SN75LVDS84ADGGR | SN75LVDS84ADGG |
|---|---|---|
| Marke | Texas Instruments | Texas Instruments |
| Kategorie | Interface ICs | Interface ICs |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $2,95 | $4,10 |
| Funktion | LVDS FlatLink 21-bit transmitter (Serializer) | FlatLink Transmitter (LVDS Serializer) |
| Number of Drivers | 4 (3 data + 1 clock) | 4 (3 data + 1 clock) |
| Datenrate | Up to 196 MBps (megabytes per second) | 196 MBps (MegaBytes per second) |
| Eingangsspannungsbereich | 3 V to 3.6 V (LVTTL single-ended) | — |
| LVDS Output Swing | Typical 350 mV differential | — |
| Number of Input Channels | 21 LVTTL data + 1 clock | — |
| Number of Output Channels | 3 LVDS data pairs + 1 LVDS clock pair | — |
| Common-Mode Range | 0 V to 2.4 V | — |
| Propagation Delay | Typical 2.5 ns | [DATA_NEEDED: tPLH / tPHL values] |
| Betriebstemperaturbereich | 0 C to +70 C | — |
| Package Type | 48-TSSOP (DGG) | — |
| Montageart | Surface Mount | Surface Mount |
| MSL-Level | 2 (1 year floor life) | [DATA_NEEDED: MSL rating] |
| RoHS-Status | Compliant | Compliant |
| Lead-Free | Yes | — |
| Family | FlatLink | — |
| AEC-Q100 Qualified | No (use SN65LVDS84AQDGG for automotive) | — |
| Parallel Inputs | — | 21 LVTTL data bits + 1 clock |
| Serial Outputs | — | 3 LVDS data pairs + 1 LVDS clock pair |
| Versorgungsspannung | — | 3.0 V to 3.6 V (3.3 V typical) |
| Supply Current (typical) | — | [DATA_NEEDED: ICC typical value] |
| LVDS Output Voltage Swing | — | [DATA_NEEDED: VOD differential swing] |
| LVTTL Input Voltage | — | [DATA_NEEDED: LVTTL input logic levels] |
| Clock Frequency Range | — | [DATA_NEEDED: parallel clock input range] |
| Betriebstemperatur | — | 0°C to +70°C (Commercial) |
| Gehäuse | — | 48-pin TSSOP (DGG) |
| Data Channel Compression | — | 21:3 (21 bits serialized over 3 differential pairs) |