SN75LVDS84ADGGR vs SN75LVDS84ADGG 对比
详细并排对比 SN75LVDS84ADGGR 出自 Texas Instruments 和 SN75LVDS84ADGG 出自 Texas Instruments。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
Texas Instruments
SN75LVDS84ADGGR - 21:3 FlatLink LVDS Transmitter 48-TSSOP | TI
SN75LVDS84ADGGR ✓ 量产中Texas Instruments
SN75LVDS84ADGG - FlatLink 21:3 LVDS Transmitter | Texas Instruments
SN75LVDS84ADGG ✓ 量产中规格对比
| 参数 | SN75LVDS84ADGGR | SN75LVDS84ADGG |
|---|---|---|
| 品牌 | Texas Instruments | Texas Instruments |
| 分类 | Interface ICs | Interface ICs |
| 生命周期状态 | 有效 | 有效 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $2.95 | $4.10 |
| 功能 | LVDS FlatLink 21-bit transmitter (Serializer) | FlatLink Transmitter (LVDS Serializer) |
| Number of Drivers | 4 (3 data + 1 clock) | 4 (3 data + 1 clock) |
| 数据速率 | Up to 196 MBps (megabytes per second) | 196 MBps (MegaBytes per second) |
| 输入电压范围 | 3 V to 3.6 V (LVTTL single-ended) | — |
| LVDS Output Swing | Typical 350 mV differential | — |
| Number of Input Channels | 21 LVTTL data + 1 clock | — |
| Number of Output Channels | 3 LVDS data pairs + 1 LVDS clock pair | — |
| Common-Mode Range | 0 V to 2.4 V | — |
| Propagation Delay | Typical 2.5 ns | [DATA_NEEDED: tPLH / tPHL values] |
| 工作温度范围 | 0 C to +70 C | — |
| Package Type | 48-TSSOP (DGG) | — |
| 安装类型 | Surface Mount | Surface Mount |
| MSL 等级 | 2 (1 year floor life) | [DATA_NEEDED: MSL rating] |
| RoHS 状态 | Compliant | Compliant |
| Lead-Free | Yes | — |
| Family | FlatLink | — |
| AEC-Q100 Qualified | No (use SN65LVDS84AQDGG for automotive) | — |
| Parallel Inputs | — | 21 LVTTL data bits + 1 clock |
| Serial Outputs | — | 3 LVDS data pairs + 1 LVDS clock pair |
| 电源电压 | — | 3.0 V to 3.6 V (3.3 V typical) |
| Supply Current (typical) | — | [DATA_NEEDED: ICC typical value] |
| LVDS Output Voltage Swing | — | [DATA_NEEDED: VOD differential swing] |
| LVTTL Input Voltage | — | [DATA_NEEDED: LVTTL input logic levels] |
| Clock Frequency Range | — | [DATA_NEEDED: parallel clock input range] |
| 工作温度 | — | 0°C to +70°C (Commercial) |
| 封装 | — | 48-pin TSSOP (DGG) |
| Data Channel Compression | — | 21:3 (21 bits serialized over 3 differential pairs) |