XC6SLX75T-2CSG484C vs XC6SLX45-2CSG484C Vergleich

Detaillierter Direktvergleich von XC6SLX75T-2CSG484C von AMD und XC6SLX45-2CSG484C von AMD. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

AMD
XC6SLX75T-2CSG484C XC6SLX75T-2CSG484C - Spartan-6 FPGA 74,637 LEs | AMD

XC6SLX75T-2CSG484C - Spartan-6 FPGA 74,637 LEs | AMD

XC6SLX75T-2CSG484C ✓ Aktiv
AMD
XC6SLX45-2CSG484C XC6SLX45-2CSG484C - Spartan-6 LX FPGA, 43,661 Logic Cells | AMD

XC6SLX45-2CSG484C - Spartan-6 LX FPGA, 43,661 Logic Cells | AMD

XC6SLX45-2CSG484C ⚠ Letzte Bestellmöglichkeit

Spezifikationsvergleich

Parameter XC6SLX75T-2CSG484C XC6SLX45-2CSG484C
Marke AMD AMD
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Aktiv Letzte Kaufgelegenheit
Lagerstatus In Stock In Stock
Stückpreis (USD) $59,50 $980,00
Family Spartan-6 LXT Spartan-6 LX
Logic Cells 74,637 —
Logic Array Blocks (LABs) 5,831 —
Adaptive Logic Modules (ALMs) 11,662 —
Total RAM Bits 3,170,304 —
User I/O Pins 292 —
Core Supply Voltage 1.2 V (1.14 V to 1.26 V) —
Process Technology 45 nm CMOS 45 nm CMOS, 9-metal copper low-k
Gehäuse 484-CSBGA (19x19 mm) 484-ball CSBGA (CSPBGA, 19 x 19 mm, 0.8 mm pitch)
Betriebstemperatur 0C to +85C —
Speed Grade -2 -2
RoHS-Status Compliant —
Montageart Surface Mount Surface Mount (BGA, requires microvia PCB)
Number of I/O Banks [DATA_NEEDED: Number of I/O Banks] —
DSP Slices [DATA_NEEDED: DSP Slices] —
Clock Management Tiles [DATA_NEEDED: Clock Management Tiles] —
Device Logic Cells — 43,661
CLBs / LABs — 3,411
Slices — 6,822
Distributed RAM (Kb) — [DATA_NEEDED: distributed RAM Kb]
Block RAM (bits) — 2,138,112 (~261 Kib)
DSP48A1 Slices — 58
User I/O Count — 320
Maximum User I/O (per datasheet) — [DATA_NEEDED: max user I/O value]
Operating Temperature (Commercial) — 0 C to +85 C
Core Supply Voltage (VCCINT) — 1.2 V (range 1.14 V to 1.26 V)
Auxiliary Supply Voltage (VCCAUX) — 3.3 V
IO Supply Voltage (VCCO) — 1.2 V to 3.3 V (per bank)
Internal Frequency (max) — 500 MHz
MSL-Level — 3 (per JEDEC J-STD-020)
RoHS / Lead-free — Compliant / Pb-free (lead-free)
Configuration Modes — JTAG, Slave Serial, SPI, BPI
Transceivers — None (LX variant; LXT variant required for GTP)

Datenblätter & Ressourcen

Alle Produkte durchsuchen BOM erstellen Angebot anfordern