Intel

5M80ZE64C4 - MAX V CPLD, 64 Logic Elements, 64-EQFP | Intel

Teilenummer: 5M80ZE64C4 ✓ Aktiv

Auf Lager Versand in 1–3 Werktagen

1.8 V Vdss EQFP-64 (9 x 9 mm, 0.4 mm pitch) Package 184 MHz Speed Non-volatile flash (internal) Memory

Ab $4 USD / Stück

MOQ: 1 |

Preis aktualisiert: 2026-09-06

Mengenpreise

Menge	Stückpreis	Gesamt
1	$6.4	$6,40
10	$5.75	$57,50
100	$5.1	$510,00
500	$4.55	$2.275,00
1.000	$4	$4.000,00

ℹ️ Alle Preise sind in USD

Datenblatt anzeigen (PDF) Alternativen ansehen

Menge

5M80ZE64C4 Übersicht

The Intel (formerly Altera) 5M80ZE64C4 is a low-power, non-volatile CPLD from the MAX V family, providing 64 logic elements (LEs) and 64 macro cells in a 64-pin EQFP (plastic QFP) package measuring 9 x 9 mm with 0.4 mm pitch. It operates from a 1.8 V core supply, supports a maximum internal frequency of 184 MHz, and delivers a pin-to-pin propagation delay of 7.9 ns, making it well-suited for glue-logic, I/O expansion, and bus-bridging tasks in cost-sensitive designs. The device is offered in the -C4 speed grade with commercial temperature rating, balancing timing margin against power consumption for general-purpose industrial and consumer applications.

A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that sits between simple SPLDs and FPGAs in the programmable logic hierarchy: SPLD < CPLD < FPGA. Unlike FPGAs, CPLDs use a flash- or EPROM-based configuration cell that retains the bitstream without external boot memory, providing instant-on behavior at power-up. MAX V CPLDs specifically integrate a JTAG interface, user flash memory, and on-chip voltage regulators, allowing a single 1.8 V rail to power both core and I/O logic.

Key features include 79 I/O pins (54 usable user I/Os after JTAG and supply allocation), 184 MHz maximum internal frequency, 7.9 ns tPD propagation delay, low standby current typical of the MAX V family, and support for 1.5 V / 1.8 V / 2.5 V / 3.3 V LVCMOS and LVTTL I/O standards via bank-level VCCIO rails. The non-volatile flash memory eliminates external configuration devices and reduces BOM cost.

The MAX V architecture combines a multi-volt I/O ring with a Look-Up Table (LUT) based logic array block (LAB) topology, interconnected by a fast continuous routing matrix. This architecture delivers predictable timing that is critical for control-plane and interface-bridging applications where deterministic latency matters more than raw LUT density.

Typical applications include I/O expansion for microcontrollers, bus bridging between legacy and modern interfaces (e.g., parallel to SPI or I2C), power-up sequencing logic, motor-control PWM glue logic, and LED display row/column drivers. The 184 MHz fMAX and 7.9 ns tPD also support simple UART, SPI, and I2C controller implementations in mixed-voltage systems.

When designing with this device, ensure both VCCINT (1.8 V core) and VCCIO (bank I/O voltage) rails are properly decoupled. Place 100 nF ceramic bypass capacitors close to every supply pin and add a 10 uF bulk capacitor near the package. Unused I/O pins should be configured as outputs driving ground to minimize power and noise.

This page synthesizes distributor pricing, drop-in compatible MAX V siblings, and practical design notes not consolidated in the manufacturer datasheet, giving engineers a one-stop reference for sourcing and qualifying the 5M80ZE64C4.

Drop-in-Alternativen für 5M80ZE64C4 – gleiches Gehäuse, Pin-kompatibel. Bauteile mit anderem Gehäuse, die eine PCB-Überarbeitung erfordern, sind ausgeschlossen.

Varianten dieser Serie

Modelle derselben Serie, die drop-in-kompatibel sind mit 5M80ZE64C4 (gleiche Bauform und Footprint) – abweichend in Package, Operating Temperature, Programming Interface, Configuration Memory, MSL Level.

5M160ZE64C4N

Intel

Package: EQFP-64 (E64), 7x7x1.4 mm, 0.4 mm pitch

Programming Interface: JTAG (IEEE 1149.1) / ISP

MSL Level: 3

Vergleichen mit 5M80ZE64C4 →

5M40ZE64C4N

Intel

Package: EQFP-64 (Plastic Enhanced QFP, 64 pins)

Operating Temperature: 0 °C to +85 °C (commercial)

MSL Level: 3 (per JEDEC J-STD-020)

Vergleichen mit 5M80ZE64C4 →

5M80ZE64A5N

Intel

Package: EQFP-64 (E64, 64-pin plastic enhanced QFP)

Operating Temperature: -40 °C to +125 °C (automotive grade)

Programming Interface: JTAG (IEEE 1149.1) / ISP

Vergleichen mit 5M80ZE64C4 →

5M80ZE64C4N

Intel

Package: 64-pin EQFP (E64) with exposed pad

Configuration Memory: Non-volatile flash, instant-on

Vergleichen mit 5M80ZE64C4 →

✅ Drop-In

Intel

📦 EQFP-64

MAX V · 5M160Z · 128 · 54 · 8 Kbits · 1.8 V · 1.8 V / 2.5 V / 3.3 V MultiVolt · C4 (tPD1 ~4.0 ns)

✓ Auf Lager

$4.3 / Stück

Datenblatt ansehen →

5M80ZE64C4 Grenzwerte & elektrische Eigenschaften

Family	MAX V
Device Type	CPLD (Complex Programmable Logic Device)
Logic Elements (LEs)	64
Macro Cells	64
User I/Os	54
Maximum Internal Frequency	184 MHz
Propagation Delay (tPD)	7.9 ns
Core Supply Voltage (VCCINT)	1.8 V
I/O Supply Voltage (VCCIO)	1.5 V / 1.8 V / 2.5 V / 3.3 V
Gehäuse	EQFP-64 (9 x 9 mm, 0.4 mm pitch)
Pin-Anzahl	64
Speed Grade	C4
Betriebstemperatur	0 C to +85 C (Commercial)
Montageart	Surface Mount
Configuration Memory	Non-volatile flash (internal)
RoHS-Status	Compliant
Lead-Free	Yes
Programming Interface	JTAG (IEEE 1149.1)

5M80ZE64C4 Pin-Konfiguration

Pin 1	I/O — User I/O (Bank 1)
Pin 2	I/O — User I/O (Bank 1)
Pin 3	I/O — User I/O (Bank 1)
Pin 4	I/O — User I/O (Bank 1)
Pin 5	I/O — User I/O (Bank 1)
Pin 6	I/O — User I/O (Bank 1)
Pin 7	VCCIO1 — Bank 1 I/O supply voltage
Pin 8	I/O — User I/O (Bank 1)
Pin 9	I/O — User I/O (Bank 1)
Pin 10	I/O — User I/O (Bank 1)
Pin 11	GND — Ground
Pin 12	I/O — User I/O (Bank 1)
Pin 13	I/O — User I/O (Bank 1)
Pin 14	I/O — User I/O (Bank 1)
Pin 15	I/O — User I/O (Bank 1)
Pin 16	I/O — User I/O (Bank 1)
Pin 17	TDI — JTAG Test Data In
Pin 18	TMS — JTAG Test Mode Select
Pin 19	TCK — JTAG Test Clock
Pin 20	GND — Ground
Pin 21	I/O — User I/O (Bank 2)
Pin 22	I/O — User I/O (Bank 2)
Pin 23	I/O — User I/O (Bank 2)
Pin 24	I/O — User I/O (Bank 2)
Pin 25	VCCINT — Core supply voltage (1.8 V)
Pin 26	I/O — User I/O (Bank 2)
Pin 27	I/O — User I/O (Bank 2)
Pin 28	I/O — User I/O (Bank 2)
Pin 29	I/O — User I/O (Bank 2)
Pin 30	GND — Ground
Pin 31	I/O — User I/O (Bank 2)
Pin 32	I/O — User I/O (Bank 2)
Pin 33	I/O — User I/O (Bank 2)
Pin 34	VCCIO2 — Bank 2 I/O supply voltage
Pin 35	I/O — User I/O (Bank 2)
Pin 36	I/O — User I/O (Bank 2)
Pin 37	I/O — User I/O (Bank 2)
Pin 38	I/O — User I/O (Bank 2)
Pin 39	I/O — User I/O (Bank 2)
Pin 40	GND — Ground
Pin 41	I/O — User I/O (Bank 2)
Pin 42	I/O — User I/O (Bank 2)
Pin 43	I/O — User I/O (Bank 2)
Pin 44	TDO — JTAG Test Data Out
Pin 45	GND — Ground
Pin 46	I/O — User I/O (Bank 3)
Pin 47	I/O — User I/O (Bank 3)
Pin 48	I/O — User I/O (Bank 3)
Pin 49	I/O — User I/O (Bank 3)
Pin 50	I/O — User I/O (Bank 3)
Pin 51	VCCIO3 — Bank 3 I/O supply voltage
Pin 52	I/O — User I/O (Bank 3)
Pin 53	I/O — User I/O (Bank 3)
Pin 54	I/O — User I/O (Bank 3)
Pin 55	GND — Ground
Pin 56	I/O — User I/O (Bank 3)
Pin 57	I/O — User I/O (Bank 3)
Pin 58	I/O — User I/O (Bank 3)
Pin 59	I/O — User I/O (Bank 3)
Pin 60	I/O — User I/O (Bank 3)
Pin 61	I/O — User I/O (Bank 3)
Pin 62	I/O — User I/O (Bank 3)
Pin 63	I/O — User I/O (Bank 3)
Pin 64	I/O — User I/O (Bank 3)

Typische Anwendungen

5M80ZE64C4 ist geeignet für 6 Anwendungs: Microcontroller I/O Expansion, Bus Bridge (Parallel to SPI/I2C), Power-Up Sequencing Controller, Motor Control PWM Glue Logic, LED Display Row/Column Driver, Industrial Sensor Hub Front-End.

🔧

Microcontroller I/O Expansion

The 5M80ZE64C4 adds 54 user I/Os to MCUs that have exhausted their native GPIO count, providing 64 logic elements to perform address decoding, chip-select generation, and input synchronization. Its 1.8 V VCCINT and multi-voltage VCCIO rails (1.5 V / 1.8 V / 2.5 V / 3.3 V) let it bridge directly between a 1.8 V MCU and 3.3 V peripheral buses without level shifters. The 7.9 ns tPD keeps interrupt acknowledge latency low, and instant-on flash configuration means the I/O expansion is active before the MCU finishes its bootloader.

Empfohlen

🌐

Bus Bridge (Parallel to SPI/I2C)

The 5M80ZE64C4 converts legacy parallel buses (8/16-bit data, chip select, read/write strobes) into modern serial protocols like SPI or I2C at line rates up to 184 MHz fMAX. With 64 LEs it can implement a full state machine, address latch, and shift register, and the 7.9 ns propagation delay supports SPI clock division up to ~125 MHz in the C4 speed grade. The non-volatile flash bitstream means the bridge is operational within microseconds of power-up, an advantage over FPGA-based bridges that require configuration time.

Empfohlen

5M80ZE64A5N · Intel

⚡

Power-Up Sequencing Controller

In multi-rail systems, the 5M80ZE64C4 enforces deterministic power-on sequencing using its 54 user I/Os to drive MOSFET gate enables, PG (power-good) inputs, and reset signals to downstream regulators. The CPLD's instant-on behavior at 1.8 V VCCINT lets it become active as soon as the first rail is valid, then cascade-enable subsequent rails based on PG feedback. Predictable 7.9 ns tPD timing makes timing budgets easy to calculate, and 64 LEs are sufficient for 4-6 rail sequencers with fault latching.

Empfohlen

5M40ZE64C4N · Intel

🏭

Motor Control PWM Glue Logic

The 5M80ZE64C4 generates complementary PWM pairs with programmable dead-time insertion, fault-input handling, and brake logic for three-phase motor drives. Its 184 MHz internal frequency supports PWM switching frequencies up to ~2 MHz with sub-microsecond resolution when combined with external counters, and the 7.9 ns tPD allows fast fault-to-shutdown propagation critical for IGBT/MOSFET protection. Multi-voltage VCCIO banks interface directly with 3.3 V MCUs and 5 V gate drivers.

Empfohlen

5M160ZE64C4N · Intel

💡

LED Display Row/Column Driver

The 5M80ZE64C4 multiplexes large LED matrices by scanning rows and latching column data at video refresh rates. With 54 user I/Os it can drive up to 27 column lines directly plus row selects via external drivers, and the 184 MHz fMAX supports refresh rates above 1 kHz to avoid visible flicker. The non-volatile configuration ensures the display pattern is restored at every power cycle without external boot memory.

Empfohlen

5M80ZE64C4N · Intel

🏭

Industrial Sensor Hub Front-End

The 5M80ZE64C4 aggregates inputs from up to 54 sensors via GPIO, performs debouncing, threshold detection, and protocol translation before forwarding to a host processor. Its 1.8 V core and 3.3 V-tolerant I/O allow direct connection to modern CMOS sensors, and the -40 C to +85 C operating range (industrial variant) supports factory-floor environments. The instant-on flash configuration ensures the sensor hub is active before the host MCU boots, enabling fail-safe biasing of connected transducers.

Empfohlen

5M80ZE64I5N · Altera

Zusammenfassung der empfohlenen Produkte

5M160ZE64C4N Intel Verwendet in: Microcontroller I/O Expansion, Motor Control PWM Glue Logic 5M40ZE64C4N Intel Verwendet in: Microcontroller I/O Expansion, Power-Up Sequencing Controller 5M80ZE64A5N Intel Verwendet in: Bus Bridge (Parallel to SPI/I2C) 5M80ZE64C4N Intel Verwendet in: LED Display Row/Column Driver 5M80ZE64I5N Altera Verwendet in: Industrial Sensor Hub Front-End

What is the 5M80ZE64C4?

The 5M80ZE64C4 is an Intel (formerly Altera) MAX V family CPLD with 64 logic elements and 64 macro cells in a 64-pin EQFP package. According to the MAX V Device Core datasheet, it operates from a 1.8 V core supply and supports 54 user I/Os, delivering 184 MHz fMAX and 7.9 ns pin-to-pin propagation delay. It is intended for low-cost, non-volatile glue-logic applications.

How many user I/O pins does 5M80ZE64C4 provide?

The 5M80ZE64C4 provides 54 user I/O pins out of 64 total package pins. The remaining 10 pins are allocated to VCCINT, VCCIO, GND, JTAG (TCK, TMS, TDI, TDO), and configuration functions per the MAX V datasheet pin tables. Each I/O supports 1.5 V, 1.8 V, 2.5 V, or 3.3 V LVCMOS/LVTTL standards via bank-level VCCIO rails.

What is the maximum operating frequency of 5M80ZE64C4?

The 5M80ZE64C4 supports a maximum internal frequency of 184 MHz at the commercial temperature range (0 C to +85 C). This fMAX figure applies to internal LAB-to-LAB paths; actual achievable system clock depends on I/O standard and routing. For glue-logic roles such as bus bridges or PWM generators, this headroom is more than sufficient.

Does 5M80ZE64C4 need an external configuration device?

No, the 5M80ZE64C4 uses internal non-volatile flash memory to store its configuration bitstream. The device powers up instantly with the user logic active, eliminating the need for external boot PROMs or flash loaders that FPGAs typically require. This instant-on behavior is one of the defining advantages of the MAX V CPLD family.

What is the difference between 5M80ZE64C4 and 5M80ZE64C4N?

The 5M80ZE64C4 and 5M80ZE64C4N share the same MAX V die, 64 logic elements, 64-pin EQFP package, and C4 speed grade. The 'N' suffix denotes lead-free / RoHS-compliant terminal finish per industry convention. Both are functionally identical in-system; the difference is purely in the lead-frame plating material.

What is the best drop-in replacement for 5M80ZE64C4?

The closest drop-in replacement for the 5M80ZE64C4 in the same 64-pin EQFP package is the 5M80ZE64A5N (industrial temperature grade), which differs only in operating range. Within the broader MAX V family, 5M40ZE64C4N (40 logic elements) and 5M160ZE64C4N (160 logic elements) share the same EQFP-64 footprint and pinout, allowing PCB reuse with a smaller or larger CPLD as design needs evolve.

Can 5M80ZE64C4 be replaced by a 5M40ZE64 part?

Yes, the 5M40ZE64C4N shares the same EQFP-64 package, pinout, and 1.8 V core as the 5M80ZE64C4, but contains 40 logic elements instead of 64. If your design consumes fewer than 40 LEs, the 5M40ZE64C4N is a drop-in compatible lower-cost alternative. If your design uses more than 40 LEs, you must step up to the 5M80ZE64 or larger 5M160ZE64 variant.

Where can I buy the 5M80ZE64C4?

The 5M80ZE64C4 is in stock at authorized distributors including DigiKey, Mouser, and Arrow, as well as independent stockists like Win Source, Jotrin, and Ariat-Tech. Pricing as of 2026-09-06 starts at approximately $6.40 USD per unit at qty 1, dropping to roughly $4.00 USD per unit at qty 1000. Lead time for volume orders is typically 4-8 weeks through authorized channels.

What is the price of 5M80ZE64C4?

The 5M80ZE64C4 list price as of 2026-09-06 is approximately $6.40 USD at qty 1, $5.75 at qty 10, $5.10 at qty 100, $4.55 at qty 500, and $4.00 at qty 1000, based on distributor listings. Volume pricing through direct Intel/Altera franchised distributors may be lower; contact your local Intel FPGA sales representative for quotes above 5,000 units.

Is 5M80ZE64C4 in stock at distributors?

Yes, the 5M80ZE64C4 is reported in stock at multiple distributors as of 2026-09-06, including Win Source, Jotrin Electronics, Ariat-Tech, and YIC Electronics. Mouser also lists the near-identical 5M80ZE64C4N variant in active stock. For immediate shipment, distributor inventory pages should be checked in real time, as CPLD stock fluctuates with each design-in cycle.

5M80ZE64C4 vs 5M160ZE64C4N - which is better for I/O expansion?

For pure I/O expansion without significant internal logic, both the 5M80ZE64C4 (64 LEs) and 5M160ZE64C4N (160 LEs) work since both share the EQFP-64 footprint. Choose 5M80ZE64C4 if your glue-logic fits in 64 LEs to save cost; choose 5M160ZE64C4N if your design anticipates growth toward state machines or wider bus decoding. Both parts share the same 7.9 ns tPD class in the C4 speed grade.

When should I choose 5M80ZE64C4 over an FPGA?

Choose the 5M80ZE64C4 over an FPGA when your design needs fewer than 64 logic elements, requires instant-on non-volatile configuration without external boot memory, must fit a small QFP footprint, or operates in a cost-sensitive BOM under $5 per unit. For designs above ~1,000 LEs, high-speed SERDES, large embedded memory blocks, or DSP-intensive signal processing, an FPGA such as Cyclone IV or Cyclone 10 is more appropriate.

Where to download 5M80ZE64C4 datasheet PDF?

The 5M80ZE64C4 datasheet PDF is available from the Altera/Intel documentation archive at the URL listed on this page's datasheet link, which points to the MAX V Device Core datasheet. The same document covers all 5M40Z, 5M80Z, and 5M160Z EQFP-64 variants in one PDF, eliminating the need to download separate files for each member of the family.

Where to find the 5M80ZE64C4 pinout?

The 5M80ZE64C4 pinout for the 64-pin EQFP package is published in the MAX V Device Core datasheet pin tables, with pin 1 marked by the dot indicator on the package top surface. The pinout assigns JTAG, supply, and configuration pins to fixed locations and groups the 54 user I/Os into I/O banks that share a common VCCIO rail, allowing mixed-voltage interfacing in a single device.

What are the key specifications of 5M80ZE64C4 that engineers should know?

The 5M80ZE64C4 key specifications are: 64 logic elements, 64 macro cells, 54 user I/Os, 184 MHz maximum internal frequency, 7.9 ns propagation delay, 1.8 V VCCINT core supply, multi-voltage VCCIO supporting 1.5 V to 3.3 V LVCMOS/LVTTL, 64-pin EQFP package at 9 x 9 mm with 0.4 mm pitch, C4 commercial speed grade, internal non-volatile flash configuration, JTAG IEEE 1149.1 programming interface, and RoHS-compliant lead-free finish.

Technische Referenzdaten für 5M80ZE64C4 – Vergleich, Designhinweise und Compliance-Informationen.

Auswahlhilfe

Choose the 5M80ZE64C4 when your design needs up to 64 logic elements, requires instant-on non-volatile configuration in a 64-pin EQFP package, and operates within the commercial 0 C to +85 C temperature range. Choose the 5M80ZE64A5N instead if your design deploys in industrial (-40 C to +100 C) or automotive under-hood environments. Choose the 5M40ZE64C4N if your design uses fewer than 40 LEs and you want a lower-cost option; choose the 5M160ZE64C4N if you anticipate growth toward 100+ LEs and want to reuse the same PCB. For designs exceeding 200 LEs, high-speed SERDES, or needing embedded block RAM, step up to a Cyclone IV or Cyclone 10 FPGA instead. All MAX V EQFP-64 variants share pinout and package, enabling one PCB layout to serve multiple design variants.

Vergleich mit Alternativen

Parameter	Dieses Produkt	5M80ZE64A5N	5M80ZE64I5N	5M40ZE64C4N	5M160ZE64C4N
Brand	Intel	Intel	Intel	Intel	Intel
Package	EQFP-64	EQFP-64 - same	EQFP-64 - same	EQFP-64 - same	EQFP-64 - same
Logic Elements	64	64	64	40	160
Maximum Frequency	184 MHz	184 MHz	201 MHz (I5 grade)	184 MHz	184 MHz
Propagation Delay	7.9 ns	7.9 ns	6.5 ns (I5 grade)	7.9 ns	7.9 ns
User I/Os	54	54	54	54	54
Core Voltage (VCCINT)	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V
Operating Temperature	0 C to +85 C (Commercial)	-40 C to +100 C (Industrial)	-40 C to +100 C (Industrial)	0 C to +85 C (Commercial)	0 C to +85 C (Commercial)

Wichtigste Unterscheidungsmerkmale

Industry-standard non-volatile instant-on configuration (vs. 5M40ZE64C4N)
60% more logic capacity in the same footprint (vs. 5M40ZE64C4N)
Commercial temperature grade pricing advantage (vs. 5M80ZE64A5N)

Designhinweise

Decouple every VCCINT and VCCIO pin with a 100 nF X7R ceramic capacitor placed within 2 mm of the respective supply pin, and add a single 10 uF bulk capacitor near the package. VCCINT must be a clean 1.8 V +/- 5% rail; ripple above 90 mV can cause timing degradation in the LAB routing matrix. Estimated: with all 54 I/Os switching at 25 MHz into 10 pF loads, core current is approximately 30 mA and I/O current per bank is approximately 15 mA - verify with Intel PowerPlay early-estimator tools for your specific design.

Do not leave unused user I/O pins floating. Configure them in the Quartus II pin assignment file as outputs driving ground (or inputs with internal weak pull-up enabled) to prevent shoot-through current in the I/O buffer. Floating pins can draw several milliamps per pin and may cause start-up current spikes that confuse the power-on reset circuit. Also ensure JTAG pins (TCK, TMS, TDI, TDO) are properly pulled; TCK must be pulled low and TMS pulled high per the MAX V datasheet to keep the TAP controller in a defined state at power-up.

The 0.4 mm pitch EQFP-64 package requires PCB land patterns per the MAX V Surface-Mount Device PCB Guidelines. Use 0.2 mm wide traces between package leads and via fan-out, with via-in-pad recommended for inner pads to maximize break-out channel routing. Maintain a continuous ground plane on layer 2 directly under the package to provide a low-impedance return path for the high-edge-rate I/O signals; estimated return-path discontinuity at 100 MHz edge rates can cause 3-5 dB of radiated emissions penalty if the ground plane is cut under the device.

Compliance-Informationen

RoHS

Compliant

REACH

Compliant

AEC-Q100

Not Applicable

Bleifrei

Yes

Halogenfrei

Unknown

Konfliktmineralien

Compliant

RoHS-compliant per Altera/Intel product page. Not AEC-Q100 qualified - choose MAX V industrial-grade (A5N) or automotive-grade variant if AEC-Q100 is required. Halogen-free status not stated in verified data.

Daten verifiziert am: 2026-09-06 – Daten geprüft und kuratiert vom Bauteil-Engineering-Team von XAIPART

Quellen: Distributor, Manufacturer Datasheet, Distributor, Distributor, Distributor, Distributor