ADS5546IRGZRG4 - 14-Bit 190MSPS ADC DDR LVDS/CMOS | TI
Teilenummer: ADS5546IRGZRG4 ✓ Aktiv| Menge | Stückpreis | Gesamt |
|---|---|---|
| 1 | $38.5 | $38,50 |
| 10 | $34.65 | $346,50 |
| 100 | $28.9 | $2.890,00 |
| 500 | $24.1 | $12.050,00 |
| 1.000 | $21.55 | $21.550,00 |
ADS5546IRGZRG4 Übersicht
An analog-to-digital converter is a data converter integrated circuit that captures continuous analog waveforms and translates them into discrete digital codes for processing by FPGAs, ASICs, DSPs, or microcontrollers. Within the broader signal chain it sits between the analog front end (amplifiers, filters) and the digital back end (logic), and the 14-bit/190-MSPS class targets intermediate-frequency sampling in communications, test and measurement, and defense imaging systems where both dynamic range and conversion speed matter.
Key features of the ADS5546 include programmable gain (0 dB, 1.5 dB, 3 dB, 6 dB) for SFDR optimization at lower input amplitudes, an internal sample-and-hold with low jitter clock buffer, internal reference with option for external reference mode, and no-missing-codes 14-bit performance. The DDR LVDS interface minimizes pin count for high-speed data capture, while a parallel CMOS mode supports legacy microcontrollers and lower-cost FPGA interfaces.
The architecture uses a pipelined core with proprietary linearity-correction techniques, supporting 1.1 W typical power dissipation at 190 MSPS from a 3.3-V analog supply and 1.8-V digital supply. The device is specified over the industrial temperature range (-40C to +85C), making it suitable for outdoor base stations, industrial instrumentation, and defense/aerospace platforms.
Typical applications include software-defined radio, broadband wireless receivers, radar signal processing, medical imaging front ends, cable-infrastructure head-end digitizers, and high-end test equipment. The 70-MHz/190-MSPS IF-sampling capability allows direct sampling of intermediate-frequency outputs from a mixer, eliminating a down-conversion stage in many communications designs.
When designing with this device, pay close attention to input network layout: a 50-ohm termination combined with a 2-pole anti-alias filter is recommended for clean IF sampling. The DDR LVDS output must be source-synchronous to the FPGA, with tightly matched trace lengths on clock and data pairs.
This page synthesizes DigiKey live inventory, TI cross-reference data, parametric alternatives, drop-in MPNs from the ADS55xx family, and practical RF/IF design notes not found in the standalone manufacturer datasheet, helping engineers shorten the BOM selection cycle.
Drop-in-Alternativen für ADS5546IRGZRG4 – gleiches Gehäuse, Pin-kompatibel. Bauteile mit anderem Gehäuse, die eine PCB-Überarbeitung erfordern, sind ausgeschlossen.
Varianten dieser Serie
Modelle derselben Serie, die drop-in-kompatibel sind mit ADS5546IRGZRG4 (gleiche Bauform und Footprint) – abweichend in Input Type, Resolution, Package, Analog Supply Voltage, Architecture.
Schnellvergleichstool – Wählen Sie Alternativbauteile für den Direktvergleich:
ADS5546IRGZ25
✅ Drop-In✓ Auf Lager
$24.95 / Stück
Datenblatt ansehen →ADS5546IRGZTG4
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
ADS5546IRGZR
✅ Drop-In✓ Auf Lager
$24.95 / Stück
Datenblatt ansehen →ADS5546IRGZT
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
ADS62P48IRGC25
✅ Drop-In✓ Auf Lager
$49.2 / Stück
Datenblatt ansehen →ADS6242IRGZR
✅ Drop-In✓ Auf Lager
$18.25 / Stück
Datenblatt ansehen →ADS5546IRGZRG4 Grenzwerte & elektrische Eigenschaften
| Auflösung | 14 bit |
| Sample Rate | 190 MSPS (max) |
| Architecture | Pipelined |
| Number of Inputs | 1 |
| Input Type | Differential |
| SNR | 73.2 dBFS at 70-MHz IF |
| SFDR | 87 dBc at 70-MHz IF, 0 dB gain |
| Output Interface | DDR LVDS / Parallel CMOS (selectable) |
| Total Power Dissipation | 1.1 W (typical at 190 MSPS) |
| Analog Supply Voltage | 3.3 V |
| Digital Supply Voltage | 1.8 V |
| Reference | Internal (external optional) |
| Sample-and-Hold | Internal |
| No Missing Codes | Yes (14-bit guaranteed) |
| Betriebstemperaturbereich | -40 C to +85 C (industrial) |
| Gehäuse | 48-VQFN (RGZ) 7x7 mm |
| Programmable Gain | 0 / 1.5 / 3 / 6 dB |
| Montageart | Surface Mount |
| MSL-Level | 3 |
| RoHS-Status | Compliant |
ADS5546IRGZRG4 48-vqfn (rgz) 7x7 mm Pinbelegungsleitfaden
Pinbelegung für ADS5546IRGZRG4 (48-vqfn (rgz) 7x7 mm-Gehäuse). Dieses analoge Bauteil verfügt über Eingangs-, Ausgangs- und Versorgungspins. Offset-Null-, Kompensations- und Enable-Pin-Konfigurationen entnehmen Sie dem Herstellerdatenblatt. Ideal für Signalaufbereitung und Verstärkerschaltungen.
Keine detaillierten Pinbelegungsdaten verfügbar für ADS5546IRGZRG4.
Siehe die Datenblatt für die vollständige Pin-Konfiguration.
Typische Anwendungen
ADS5546IRGZRG4 ist geeignet für 7 Anwendungs: Software-Defined Radio / Wideband Receiver, Radar / Defense Signal Processing Front End, Medical Imaging Front End (Ultrasound / MRI Receiver), Cable Infrastructure / Headend Digitizer, Test and Measurement Instrumentation, Broadband Wireless Base Station Receiver, Industrial Data Acquisition.
Software-Defined Radio / Wideband Receiver
The ADS5546IRGZRG4 supports direct IF sampling in software-defined radio receivers up to 70 MHz. Its 14-bit resolution at 190 MSPS delivers 73.2-dBFS SNR, sufficient for demodulating QAM and OFDM waveforms below the FPGA. Used after a passive anti-alias filter and TI THS4509 differential amplifier front-end, the ADS5546's DDR LVDS output feeds directly into an FPGA LVDS deserializer with matched-length traces. Compared with discrete 2-stage down-conversion, this single-IF topology saves PCB area, BOM cost, and reduces group-delay distortion. Pair with a CDCE62002 clocking IC for low-jitter performance and Xilinx Kintex-7 for baseband DSP.
Empfohlen
Radar / Defense Signal Processing Front End
In radar and electronic-warfare front ends, the ADS5546IRGZRG4 digitizes 70-MHz IF outputs from a mixer with 87-dBc SFDR, preserving the dynamic range of pulse-compressed waveforms. The industrial -40C to +85C temperature range suits outdoor and military installations; the 48-VQFN RGZ package's exposed thermal pad conducts heat to the inner PCB layer for sustained 1.1 W dissipation. Used as the digitizer behind a SAW bandpass filter and LNA, it feeds an FPGA-based FFT pipeline. Its pipelined core introduces deterministic latency suited to matched-filter designs, and the programmable gain (0/1.5/3/6 dB) lets the radar receiver trade off clipping margin versus SFDR.
Empfohlen
Medical Imaging Front End (Ultrasound / MRI Receiver)
Ultrasound and MRI receiver arrays digitize IF signals close to the LNA output to minimize analog chain length. The ADS5546IRGZRG4's 14-bit resolution and 73.2-dBFS SNR preserve the linear dynamic range needed for grayscale tissue differentiation, while 190 MSPS exceeds typical 40-MHz ultrasound IF bandwidth. The device's internal sample-and-hold and low-jitter clock buffer reduce component count compared with multi-chip receivers. The CMOS output mode is particularly valuable in multi-channel array designs where LVDS trace density becomes prohibitive; the device can be parallel-CMOS-clocked into a low-cost FPGA per channel.
Empfohlen
Cable Infrastructure / Headend Digitizer
Cable-TV headend equipment digitizes QAM-modulated channels in the 50-1000 MHz range using sub-band IF sampling. The ADS5546IRGZRG4's 190-MSPS throughput enables a single ADC to digitize a 70-MHz IF carrying multiple digital video broadcast channels, while its DDR LVDS output streams into Xilinx or Altera FPGAs at the rate demanded by DOCSIS 3.1 receivers. The 1.1 W power budget fits headend-card thermal envelopes of approximately 8 W per slot. Combined with TI's TRF3703 quadrature modulator and LMH6517 variable-gain driver, designers build a complete digital-IF cable receiver with deterministic channel flatness across the 1-GHz spectrum.
Empfohlen
Test and Measurement Instrumentation
Modern oscilloscopes, spectrum analyzers, and signal analyzers use wideband ADCs at the input stage. The ADS5546IRGZRG4's 190 MSPS and 73.2-dBFS SNR suit a 100-MHz real-time bandwidth oscilloscope or a digital spectrum analyzer. Its programmable gain (0/1.5/3/6 dB) lets the instrument digitize small signals with improved SFDR while remaining within full-scale at peak amplitudes. The 48-VQFN package fits densely populated instrument mainboards. Designers pair the ADC with TI's THS4631 FET-input buffer and a high-stability TCXO clock for laboratory-grade phase-noise performance.
Empfohlen
Broadband Wireless Base Station Receiver
GSM, LTE, and 5G base-station receivers digitize IF signals at 70 MHz with high dynamic range. The ADS5546IRGZRG4 delivers 73.2-dBFS SNR and 87-dBc SFDR - sufficient to discriminate weak pilot channels from a strong interferer in dense urban cells. The 1.1 W dissipation at 190 MSPS keeps per-channel power within the thermal envelope of remote-radio-head (RRH) outdoor units. The DDR LVDS interface supports sampling-rate flexibility from 80 to 190 MSPS across multiple air-interface standards. Pair with TI's GC5328 digital pre-distortion processor and TRF3765 synthesizer for a complete multi-standard radio chain.
Empfohlen
Industrial Data Acquisition
High-speed industrial digitizers for vibration, machine-health monitoring, and acoustic-emission testing benefit from the ADS5546IRGZRG4's combination of 14-bit resolution and 190 MSPS. The industrial -40C to +85C temperature range qualifies the part for outdoor enclosures and factory-floor installations where ambient temperatures vary widely. The internal sample-and-hold eliminates the need for an external track-and-hold amplifier, reducing BOM cost and layout area. Engineers use the parallel CMOS output mode when feeding legacy microcontrollers or DSPs without LVDS I/O, simplifying designs in cost-sensitive factory-automation deployments.
Empfohlen
Zusammenfassung der empfohlenen Produkte
Technische Referenzdaten für ADS5546IRGZRG4 – Vergleich, Designhinweise und Compliance-Informationen.
Auswahlhilfe
Vergleich mit Alternativen
| Parameter | Dieses Produkt | ADS5546IRGZ25 | ADS5546IRGZTG4 | ADS5546IRGZR | ADS5546IRGZT |
|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 48-VQFN (RGZ) 7x7 mm | 48-VQFN (RGZ) 7x7 mm - same | 48-VQFN (RGZ) 7x7 mm - same | 48-VQFN (RGZ) 7x7 mm - same | 48-VQFN (RGZ) 7x7 mm - same |
| Resolution | 14 bit | 14 bit | 14 bit | 14 bit | 14 bit |
| Sample Rate | 190 MSPS | 190 MSPS | 190 MSPS | 190 MSPS | 190 MSPS |
| SNR at 70-MHz IF | 73.2 dBFS | 73.2 dBFS | 73.2 dBFS | 73.2 dBFS | 73.2 dBFS |
| SFDR at 70-MHz IF | 87 dBc | 87 dBc | 87 dBc | 87 dBc | 87 dBc |
| Output Interface | DDR LVDS / Parallel CMOS (selectable) | DDR LVDS / Parallel CMOS | DDR LVDS / Parallel CMOS | DDR LVDS / Parallel CMOS | DDR LVDS / Parallel CMOS |
| Power Dissipation | 1.1 W | 1.1 W | 1.1 W | 1.1 W | 1.1 W |
| Operating Temperature | -40 C to +85 C (industrial) | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C |
Wichtigste Unterscheidungsmerkmale
- 190-MSPS throughput at 14-bit resolution (vs. ADS6242IRGZR (12-bit 65 MSPS))
- DDR LVDS / CMOS selectable output interface (vs. ADS5103IPFBRG4 (low-speed CMOS-only))
- Industrial -40C to +85C operating temperature range (vs. Commercial-grade ADCs)
Designhinweise
The ADS5546's DDR LVDS output requires a source-synchronous interface to the FPGA. Use tightly matched trace lengths (clock-to-data skew tolerance typically 250 ps per datasheet) and 100-ohm differential impedance at the FPGA LVDS pins. Insert 100-ohm termination across each LVDS pair at the FPGA side. Skew mismatches cause bit errors in DDR data capture and will appear as elevated noise floor in FFT analysis.
Estimated: at 190 MSPS, 3.3 V analog supply, and 1.1 W typical dissipation, the supply current on AVDD is roughly 250 mA and on DRVDD another 100 mA. Decouple AVDD with 10 uF tantalum plus 100 nF ceramic at each supply pin; pin-by-pin 100 nF capacitors are mandatory. Keep analog/digital ground planes separated until they join under the exposed pad, using a star-ground topology. Power-supply rejection is specified at the datasheet's decoupling recommendation only.
Use a 6-layer PCB with solid ground plane layers placed adjacent to the top signal layer for the 48-VQFN. The exposed thermal pad (EP) must be soldered to a 10x10 thermal pad with 9 thermal vias (0.3 mm drill on 1-mm pitch) connecting to inner ground. Failure to solder the EP voids the thermal path and reduces reliability at the +85 C upper operating range. Route clock traces on a dedicated inner stripline layer.
Place a 50-ohm termination resistor on the analog input network as close to the ADC pins as possible (within 5 mm). Use a balanced, transformer-coupled input with a 1:1 ratio (e.g., Mini-Circuits ADT1-1WT or equivalent) to convert the single-ended IF to the differential format the ADC expects. Keep clock traces away from analog inputs to avoid coupling; cross clock and analog traces at 90 degrees if they must intersect.
Do not exceed the maximum sampling rate beyond 190 MSPS - timing margin in the DDR LVDS interface is reduced and bit-error rate increases rapidly. Do not omit the external reference-mode bypass capacitor even in internal-reference mode; the internal reference needs 10 uF + 100 nF decoupling per the datasheet. Do not use the parallel CMOS mode beyond 100 MSPS - output skew exceeds timing budget above that sample rate.
Compliance-Informationen
RoHS compliant per TI product page. ADS5546 is not AEC-Q100 qualified - for automotive ADC applications TI offers the ADS62P28 family in a 64-VQFN. The -G4 suffix designates tape-and-reel orientation only and does not affect compliance.
