AOZ5517QI-03 - 60A DrMOS Smart Power Stage | AOS
Teilenummer: AOZ5517QI-03 ✓ Aktiv| Menge | Stückpreis | Gesamt |
|---|---|---|
| 1 | $1.85 | $1,85 |
| 10 | $1.67 | $16,70 |
| 100 | $1.42 | $142,00 |
| 500 | $1.21 | $605,00 |
| 1.000 | $1.05 | $1.050,00 |
AOZ5517QI-03 Übersicht
DrMOS is a DrMOS-compatible integrated power stage that combines the high-side MOSFET, low-side MOSFET, and gate driver in a single optimized package, reducing parasitic inductance and loop area compared with discrete implementations. By driving the two MOSFETs from a co-located driver IC, dead-time loss is minimized, switching edges are sharpened, and PCB real estate drops dramatically versus a discrete buck stage. This category belongs to the broader family of voltage regulators (DC-DC converters, smart power stages) within power management ICs.
Key electrical characteristics include 60 A continuous output current capability, an integrated bootstrap diode, and adaptive dead-time control to prevent cross-conduction. The device supports Tri-State PWM logic, FCCM forced-continuous-current mode for transient response, and PWM mode for light-load efficiency. Built-in protection features include over-temperature, over-current, and fault output signaling to the controller for graceful system response.
The power stage uses AOS's proprietary trench MOSFET technology with the high-side FET optimized for low gate charge and fast switching at low duty cycle, and the low-side FET optimized for ultra-low Rds(on) to minimize conduction loss. The exposed top-side thermal pad delivers a low thermal-resistance path to PCB copper, supporting sustained high-current operation in space-constrained designs.
Typical applications for the AOZ5517QI-03 include high-current single-phase and multi-phase CPU/SoC core voltage regulators in notebooks and servers, graphics-card VCORE rails, point-of-load converters in telecom switches, and high-current POL modules for AI accelerators. The integrated design dramatically shrinks BOM count and simplifies PCB layout versus an equivalent discrete synchronous buck stage.
When designing with this device, ensure the 5 V bias supply (VCC) is decoupled with a 1 uF X5R/X7R ceramic placed within 25 mm of the VCC pin. The exposed thermal pad must be soldered to a continuous ground plane with thermal vias; otherwise junction temperature will rise quickly at 30 A+ loads. Avoid routing the BOOT trace under the high-side MOSFET to prevent dv/dt coupling.
This page synthesizes distributor pricing, drop-in pin-compatible alternatives (same QFN5x5-31L footprint), and practical layout/design notes not directly aggregated in any individual manufacturer datasheet.
Drop-in-Alternativen für AOZ5517QI-03 – gleiches Gehäuse, Pin-kompatibel. Bauteile mit anderem Gehäuse, die eine PCB-Überarbeitung erfordern, sind ausgeschlossen.
Schnellvergleichstool – Wählen Sie Alternativbauteile für den Direktvergleich:
AOZ5517QI
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
AOZ55073QI
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
AOZ55973QI
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
NCP526050
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
CSD95492QVM
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
AOZ5517QI-03 Grenzwerte & elektrische Eigenschaften
| Topologie | Synchronous buck power stage (DrMOS) |
| Input Voltage Range (VIN) | 4.5 V to 25 V |
| Driver Supply Voltage (VCC) | 5 V (typ) |
| Continuous Output Current | 60 A |
| PWM Input Logic | 5 V CMOS, Tri-State |
| Control Modes | PWM and FCCM (Forced Continuous Current Mode) |
| Bootstrap Diode | Integrated |
| Betriebstemperatur | -40 C to +125 C |
| Gehäuse | QFN5x5-31L Power Module (5 x 5 mm) |
| Montageart | Surface Mount with exposed thermal pad |
| RoHS-Status | Compliant |
| Fault Output | Yes (open-drain) |
| Protection Features | Over-temperature, Over-current, UVLO |
AOZ5517QI-03 Pin-Konfiguration
| Pin 1 | VIN — Power input to high-side MOSFET drain (4.5-25 V) |
| Pin 2 | VIN — Power input to high-side MOSFET drain |
| Pin 3 | VIN — Power input to high-side MOSFET drain |
| Pin 4 | PHASE — Switch node to high-side source / low-side drain |
| Pin 5 | PHASE — Switch node return |
| Pin 6 | PHASE — Switch node return |
| Pin 7 | LGATE — Low-side gate driver output (use only as test point) |
| Pin 8 | PGND — Power ground (low-side MOSFET source return) |
| Pin 9 | PGND — Power ground |
| Pin 10 | PGND — Power ground |
| Pin 11 | NC — Not connected (per datasheet) |
| Pin 12 | VCC — Gate-driver 5 V bias supply |
| Pin 13 | FCCM — Forced Continuous Current Mode logic input |
| Pin 14 | PWM — Tri-State PWM control input (5 V CMOS) |
| Pin 15 | PGND — Power ground / signal ground |
| Pin 16 | NC — Not connected (per datasheet) |
| Pin 17 | NC — Not connected (per datasheet) |
| Pin 18 | TSENSE — Thermal sense / temperature flag analog output |
| Pin 19 | NC — Not connected (per datasheet) |
| Pin 20 | FAULT — Open-drain fault output flag (active low) |
| Pin 21 | NC — Not connected (per datasheet) |
| Pin 22 | NC — Not connected (per datasheet) |
| Pin 23 | NC — Not connected (per datasheet) |
| Pin 24 | NC — Not connected (per datasheet) |
| Pin 25 | NC — Not connected (per datasheet) |
| Pin 26 | UGATE — High-side gate driver output (test point only) |
| Pin 27 | BOOT — Bootstrap supply for high-side driver |
| Pin 28 | BOOT — Bootstrap supply |
| Pin 29 | BOOT — Bootstrap supply |
| Pin 30 | VIN — Power input to high-side MOSFET drain |
| Pin 31 | PAD — Exposed thermal pad - must be soldered to power ground copper |
Typische Anwendungen
AOZ5517QI-03 ist geeignet für 7 Anwendungs: CPU/SoC Core Voltage Regulator (Notebook & Server), Graphics Card VCORE / GPU Power Rail, Telecom Switch / Router Point-of-Load Modules, AI Accelerator Card POL Stages, Industrial High-Current DC-DC Modules, Single-Phase 60 A POL Module (DDR / ASIC Memory Rails), High-Current Buck Battery Charger / PowerPath Stage.
CPU/SoC Core Voltage Regulator (Notebook & Server)
The AOZ5517QI-03 is designed primarily as a power stage for CPU/GPU/SoC Vcore rails in notebook and server platforms. Its 60 A continuous current rating and 4.5 V-25 V input range match the 12 V system bus and 5 V bias typical of Intel/AMD Vcore designs, while its Tri-State PWM interface is compatible with multi-phase VR controllers such as the AOS AOZ1267/AOZ1268 and TI TPS53679. Paired with a 4-phase or 6-phase controller, four or six AOZ5517QI-03 stages deliver 240 A-360 A to a server-class CPU. Compared with discrete MOSFET-driver approaches, the integrated DrMOS shrinks PCB area by roughly 60 % and eliminates about 12-15 components per phase.
Empfohlen
Graphics Card VCORE / GPU Power Rail
GPU core voltage rails on mid- to high-end graphics cards demand 60-200 A transient currents, exactly what the AOZ5517QI-03 is built to handle. The high-side MOSFET is optimized for low duty-cycle switching at high frequency, while the low-side FET is designed for ultra-low Rds(on) to minimize conduction loss during full-load graphics rendering. The exposed top-side thermal pad allows direct PCB copper cooling while keeping the GPU board footprint compact. Designers typically parallel two or three AOZ5517QI-03 stages per GPU to deliver 120-180 A peak transient currents during gaming or compute workloads.
Empfohlen
Telecom Switch / Router Point-of-Load Modules
Telecom switches and edge routers require isolated DC-DC brick distributions to 12 V followed by high-efficiency point-of-load (POL) rails at 1 V or less for switching ASICs. The AOZ5517QI-03's 25 V max input suits 12 V intermediate bus architectures directly, and its 60 A continuous output is well-matched to typical 25-40 A POL rails (over-designed for headroom). The integrated bootstrap diode reduces BOM, and adaptive dead-time control minimizes switching loss at the higher switching frequencies used in dense telecom boards. Fault output flagging lets the system controller implement graceful shutdown on thermal events.
Empfohlen
AI Accelerator Card POL Stages
AI accelerator ASICs in HPC and edge inference cards require high-current, low-voltage core rails with extremely tight regulation, and the AOZ5517QI-03's DrMOS integration delivers exactly that footprint. With 60 A per phase and sub-1 us transient response, a single AOZ5517QI-03 can power a 1.8 V/50 A accelerator sub-rail directly from a 12 V intermediate bus, while a 4-phase configuration delivers 200+ A for the largest AI dice. The integrated fault output enables OR-ing with redundant power paths, important in 24/7 datacenter applications. Designers typically use FCCM mode to avoid output ripple bursts during accelerator idle states.
Empfohlen
Industrial High-Current DC-DC Modules
Beyond computing, the AOZ5517QI-03 is well-suited to industrial high-current DC-DC modules such as motor-drive auxiliary supplies, PLC backplane 5 V/24 V POL converters, and battery management sub-systems. The device's -40 C to +125 C operating range covers industrial temperature class, while its 4.5 V minimum input supports 5 V hold-up conditions after brownouts. The integrated bootstrap diode and adaptive dead-time control reduce the controller-side complexity, letting designers focus on electromagnetic compliance (EMC) and failure-mode analysis. The exposed thermal pad supports heat-sinking to chassis ground or PCB inner-layer copper.
Empfohlen
Single-Phase 60 A POL Module (DDR / ASIC Memory Rails)
Memory rail voltages such as DDR5 VDDQ (1.1 V) and ASIC auxiliary rails (typically 0.8-1.5 V at 30-50 A) are a clean fit for the AOZ5517QI-03 in a single-phase configuration. Compared with a discrete buck using two FETs and a driver IC, the integrated DrMOS simplifies layout, reduces parasitic loop inductance by 4-5x, and improves transient response (often 2x faster load step settling). The 5 V VCC bias can be derived from an upstream LDO, simplifying sequencing. Designers benefit from the FCCM mode option to maintain tight regulation across all load currents in memory subsystems.
Empfohlen
High-Current Buck Battery Charger / PowerPath Stage
Although primarily a Vcore stage, the AOZ5517QI-03's two-MOSFET + integrated driver topology maps cleanly onto high-current buck battery-charger or USB-PD sub-rails in dock/portable applications. With 60 A capability and 25 V max input, a single stage can step 20 V PD input down to 12 V/5 A or 5 V/20 A battery charge rails. The Tri-State PWM input accepts standard buck-controller signals, while the FCCM mode maintains light-load regulation. Designers must derate for continuous battery-charge duration vs. peak Vcore load duty cycles.
Empfohlen
Zusammenfassung der empfohlenen Produkte
Technische Referenzdaten für AOZ5517QI-03 – Vergleich, Designhinweise und Compliance-Informationen.
Auswahlhilfe
Vergleich mit Alternativen
| Parameter | Dieses Produkt | AOZ5517QI | AOZ55073QI | AOZ55973QI | NCP526050 | CSD95492QVM |
|---|---|---|---|---|---|---|
| Brand | Alpha & Omega Semiconductor | Alpha & Omega Semiconductor | Alpha & Omega Semiconductor | Alpha & Omega Semiconductor | onsemi | Texas Instruments |
| Package | QFN5x5-31L | QFN5x5-31L (same) | QFN5x5-31L (same) | QFN5x5-31L (same) | QFN5x5-31L (same) | QFN5x5-31L (same) |
| Continuous Output Current | 60 A | 60 A (same) | 60 A (same) | 60 A (same) | 60 A (same) | 60 A (same) |
| Input Voltage Range | 4.5 V to 25 V | 4.5 V to 25 V (same) | 4.5 V to 25 V (same) | 4.5 V to 25 V (same) | 4.5 V to 25 V (same) | 4.5 V to 25 V (same) |
| PWM Interface | Tri-State 5 V CMOS | Tri-State 5 V CMOS (same) | Tri-State 5 V CMOS (same) | Tri-State 5 V CMOS (same) | Tri-State 5 V CMOS (same) | Tri-State 5 V CMOS (same) |
| Bootstrap Diode | Integrated | Integrated (same) | Integrated (same) | Integrated (same) | Integrated (same) | Integrated (same) |
| Optimized Frequency | Up to ~600 kHz | Up to ~600 kHz (same) | >700 kHz (higher freq) | ~600 kHz to 1 MHz | Up to ~1 MHz | Up to ~1.5 MHz |
| Fault Output | Yes (open-drain) | Yes (same) | Yes (same) | Yes (same) | Yes (same) | Yes (same) |
| Application Class | CPU/GPU Vcore, POL | CPU/GPU Vcore, POL (same) | High-frequency Vcore/POL | CPU/GPU Vcore, POL | Server and graphics Vcore | Server Vcore, datacenter POL |
Wichtigste Unterscheidungsmerkmale
- 60 A continuous output in a 5x5 mm footprint (vs. Discrete MOSFET + discrete gate driver)
- Tri-State PWM with FCCM mode option (vs. AOZ55073QI)
- Standardized 31-lead DrMOS land pattern (vs. NCP526050 (onsemi))
- Light-load efficiency optimization (vs. AOZ55073QI)
Designhinweise
Estimated: At full-load operation of 60 A at VIN=12 V, VOUT=1 V, the AOZ5517QI-03 dissipates roughly (12 V - 1 V) x 60 A x (1 - efficiency) of conduction+switching loss. With typical 92-94 % peak efficiency at 300 kHz, total module loss is around 4-5 W. The exposed thermal pad (pin 31) MUST be soldered to a continuous top-layer power-ground pour connected by an array of 0.3 mm thermal vias to inner-layer ground planes. Without proper thermal management, junction temperature will quickly exceed 125 C and the over-temperature flag will trigger, shutting down the regulator.
Place the VCC (5 V bias) decoupling capacitor within 25 mm of pin 12, using at minimum 1 uF X5R or X7R 0402/0603 ceramic. Add a 0.1 uF high-frequency bypass in parallel. The bootstrap capacitor (typically 0.1 uF to 1 uF X7R) must sit between BOOT (pin 27-29) and PHASE (pin 4-6) with the shortest possible trace length to minimize dv/dt-induced voltage ringing. Do NOT route the BOOT trace under the high-side MOSFET - dv/dt coupling will disrupt gate drive. Keep high-current VIN and PGND return loops as short and wide as possible to minimize parasitic inductance.
Route the high-current VIN nets on inner layers or the top copper pour directly into pins 1-3 and 30. Use a star-ground topology where AGND from the controller terminates at the AOZ5517QI-03's PGND pin (15) - mixing AGND and PGND at the module can introduce ground-loop noise and false triggering of the fault comparator. Place the controller IC within 50 mm of the PWM input to avoid PWM signal degradation; use a series resistor (10 ohm to 33 ohm) at the PWM pin to damp any ringing on long traces.
Common pitfalls to avoid: (1) Operating above 25 V VIN - the device is only rated to 25 V; stress above this may damage the high-side MOSFET. (2) Driving PWM with a 3.3 V signal without a translator logic level - the AOZ5517QI-03 requires a 5 V CMOS signal to recognize PWM high; an under-driven input is sometimes interpreted as Tri-State. (3) Forgetting to tie FCCM to VCC or GND - a floating FCCM pin can cause unpredictable operation; pull it high for FCCM, low for diode emulation. (4) Sharing a single 5 V VCC bias between two AOZ5517QI-03 stages without sufficient bypass capacitance; each stage should have its own decoupling.
Compliance-Informationen
RoHS and REACH compliant per AOS product page. AEC-Q100 not applicable - this part is a power stage for compute platforms, not automotive. Lead-free and halogen-free packaging confirmed.
