CP2104-F03-GMR - USB 2.0 to UART Bridge QFN-24 | Silicon Labs
Teilenummer: CP2104-F03-GMR ✓ Aktiv| Menge | Stückpreis | Gesamt |
|---|---|---|
| 1 | $1.62 | $1,62 |
| 10 | $1.46 | $14,60 |
| 100 | $1.31 | $131,00 |
| 500 | $1.18 | $590,00 |
| 1.000 | $1.06 | $1.060,00 |
CP2104-F03-GMR Übersicht
A USB-to-UART bridge is an interface IC that converts USB bus traffic into a standard asynchronous serial (UART) stream, allowing a host computer to communicate with embedded microcontrollers over a virtual COM port. Within the power-management and interface-IC hierarchy, it sits between the physical USB layer and the MCU serial peripheral, eliminating firmware development on the bridge side.
Key features include a fully integrated USB transceiver (no external resistors), an integrated clock (no external crystal), a programmable baud rate from 300 bps to 2 Mbps, 1024 bytes of one-time-programmable ROM for custom VID/PID and product strings, and royalty-free virtual COM port drivers for Windows, macOS, and Linux. Four GPIO pins (GPIO.0 to GPIO.3) with hardware flow control (~RTS/~CTS, ~DTR/~DSR, ~DCD/~RI) provide flexible signaling.
Architecturally, the CP2104 pairs a USB 2.0 full-speed (12 Mbps) device controller with a UART engine and on-chip power-on-reset circuitry. The integrated 3.45 V regulator can supply external circuitry at modest current, and SUSPEND/~SUSPEND outputs support USB bus power management.
Typical applications include USB-to-serial programming and debug adapters, MCU bootloaders for kits such as ESP32 and Arduino-style boards, industrial controllers and data loggers, and embedded computing modules needing a plug-and-play serial link.
Design tip: keep the 4.7 uF to 10 uF decoupling on VDD/VBUS close to the pins, connect REGIN to VBUS, and bias ~RST high with 4.7 kohm to avoid spurious enumeration resets. VIO lets the UART side interface with 1.8 V logic without level shifting.
This page synthesizes distributor pricing, drop-in alternatives, pinout, and practical design notes not found in the manufacturer datasheet alone. Pricing shown as of 2026-10-20.
Drop-in-Alternativen für CP2104-F03-GMR – gleiches Gehäuse, Pin-kompatibel. Bauteile mit anderem Gehäuse, die eine PCB-Überarbeitung erfordern, sind ausgeschlossen.
Varianten dieser Serie
Modelle derselben Serie, die drop-in-kompatibel sind mit CP2104-F03-GMR (gleiche Bauform und Footprint) – abweichend in Package, USB Standard, Function, GPIO, Integrated USB Transceiver.
Schnellvergleichstool – Wählen Sie Alternativbauteile für den Direktvergleich:
CP2104-F03-GM
✅ Drop-In✓ Auf Lager
$1.62 / Stück
Datenblatt ansehen →CP2103-GM
✅ Drop-In✓ Auf Lager
$7.0886 / Stück
Datenblatt ansehen →CP2103-GMR
✅ Drop-In✓ Auf Lager
Preis auf Anfrage
Datenblatt ansehen →CP2105-F01-GM
✅ Drop-In✓ Auf Lager
$2.4776 / Stück
Datenblatt ansehen →CP2105-F01-GMR
✅ Drop-In✓ Auf Lager
$2.1114 / Stück
Datenblatt ansehen →CP2110-F01-GM
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
CP2104-F03-GMR Technische Daten
| Funktion | USB 2.0 to UART bridge controller |
| USB Standard | USB 2.0 full speed, 12 Mbps |
| UART Channels | 1 |
| Baud Rate Range | 300 bps to 2 Mbps (programmable) |
| FIFO Buffer | 576 byte |
| Versorgungsspannung | 3 V to 3.6 V (VDD) |
| I/O Supply (VIO) | 1.8 V, 3 V to 3.6 V |
| On-Chip Regulator Output | 3.45 V |
| Non-Volatile Memory | 1024 byte one-time-programmable ROM |
| GPIO | 4 digital I/O pins |
| Flow Control | ~RTS, ~CTS, ~DTR, ~DSR, ~DCD, ~RI |
| Gehäuse | 24-QFN (4x4 mm) with exposed pad |
| Montageart | Surface Mount |
| Betriebstemperatur | -40C to +85C |
| Integrated Clock | Yes (no external crystal required) |
| Integrated USB Transceiver | Yes (no external resistors required) |
| Power-On Reset | On-chip |
| RoHS-Status | Compliant |
CP2104-F03-GMR Pin-Konfiguration
| Pin 1 | ~RI — Ring Indicator input (modem signal, active low) |
| Pin 2 | GND — Ground |
| Pin 3 | D+ — USB 2.0 differential data plus |
| Pin 4 | D- — USB 2.0 differential data minus |
| Pin 5 | VIO — I/O supply for UART-side interface (1.8 V to 3.6 V) |
| Pin 6 | VDD — Power supply, 3.0 V to 3.6 V |
| Pin 7 | REGIN — Regulator input, connect to VBUS (4.0 V to 5.25 V) |
| Pin 8 | VBUS — USB bus voltage sense input |
| Pin 9 | ~RST — Device reset, active low; pull up with 4.7 kohm |
| Pin 10 | NC — Not connected (per datasheet) |
| Pin 11 | GPIO.3 — General purpose I/O 3 |
| Pin 12 | GPIO.2 — General purpose I/O 2 |
| Pin 13 | GPIO.1 — General purpose I/O 1 |
| Pin 14 | GPIO.0 — General purpose I/O 0 |
| Pin 15 | ~SUSPEND — Suspend indicator, active low |
| Pin 16 | VPP — OTP ROM programming voltage (leave unconnected in application) |
| Pin 17 | ~SUSPEND — Complementary suspend indicator |
| Pin 18 | ~CTS — Clear To Send input (hardware flow control, active low) |
| Pin 19 | ~RTS — Request To Send output (hardware flow control, active low) |
| Pin 20 | RXD — UART receive data input |
| Pin 21 | TXD — UART transmit data output |
| Pin 22 | ~DSR — Data Set Ready input (modem signal, active low) |
| Pin 23 | ~DTR — Data Terminal Ready output (modem signal, active low) |
| Pin 24 | ~DCD — Data Carrier Detect input (modem signal, active low) |
Typische Anwendungen
CP2104-F03-GMR ist geeignet für 6 Anwendungs: MCU Programming and Debug Adapters, Industrial Controllers and Data Loggers, USB Virtual COM Port Dongles, Embedded Computing and IoT Gateways, Point-of-Sale and Payment Terminals, Medical Device Diagnostics Ports.
MCU Programming and Debug Adapters
The CP2104-F03-GMR is the de-facto USB-to-serial interface on ESP32, ESP8266, and many ARM Cortex-M development boards because its 2 Mbps ceiling covers all common ROM bootloader speeds and its 576-byte FIFO absorbs burst transfers during firmware flashing without dropping bytes. On the PCB it sits directly between the USB connector and the MCU's UART pins, with auto-program circuitry (DTR/RTS transistor networks) driving the MCU's EN/IO0 strapping. Because the transceiver and clock are integrated, an adapter can be built with just the CP2104, three decoupling capacitors, and an ~RST pull-up, yielding a very low BOM cost for production programmers.
Empfohlen
Industrial Controllers and Data Loggers
In industrial controllers, the CP2104-F03-GMR provides a service port that field technicians use to reconfigure setpoints or dump logs over a standard USB cable. The -40C to +85C operating range and on-chip power-on-reset ensure reliable enumeration across factory floor temperature extremes, while the 1024-byte OTP ROM lets OEMs program a custom VID/PID so their service tool enumerates with a company-specific device name. Hardware flow control (~RTS/~CTS) protects logged data during long transfers, and the SUSPEND/~SUSPEND outputs allow the logger to gate its own peripherals when the host sleeps, cutting quiescent power in bus-powered installations.
Empfohlen
USB Virtual COM Port Dongles
Standalone USB-to-UART dongles are the highest-volume application for the CP2104-F03-GMR. Because it enumerates as a virtual COM port with royalty-free drivers on Windows, macOS, and Linux, end users get plug-and-play serial connectivity without installation. The integrated 3.45 V regulator powers the bridge directly from VBUS, so a bus-powered dongle needs no LDO; VIO can be jumpered to 1.8 V, 3.3 V, or the regulator output to make a multi-voltage adapter. The 12 Mbps USB full-speed link is not the bottleneck for UART traffic at any baud rate up to 2 Mbps, and the exposed-pad QFN-24 dissipates heat readily in an enclosed plastic shell.
Empfohlen
Embedded Computing and IoT Gateways
IoT gateways and single-board computers use the CP2104-F03-GMR as the console UART bridge exposing the SoC's debug serial port on a USB micro-B or Type-C receptacle. The 1.8 V VIO capability is key here: modern application processors run console UARTs at 1.8 V logic, and connecting VIO to the SoC rail lets the CP2104 interface directly without a level shifter, saving board area. Its small 4x4 mm QFN-24 footprint fits dense gateway PCBs, and the OTP ROM allows OEMs to ship a branded console port name in device manager, improving support triage. Full modem signals support consoles that require hardware handshaking.
Empfohlen
Point-of-Sale and Payment Terminals
Payment terminals and POS peripherals frequently pair the CP2104-F03-GMR with secure elements and receipt printers that still communicate over UART. The bridge's 576-byte FIFO keeps transaction data intact under host scheduling jitter, and hardware flow control lines (~DTR/~DSR, ~DCD/~RI) map naturally onto legacy peripheral protocols that expect full modem signaling. Because the device enumerates with a stable, well-supported driver stack across POS terminal operating systems, integration risk is low. The OTP ROM supports per-unit serialization, which integrators use for asset tracking and tamper-evidence audits across terminal fleets.
Empfohlen
Medical Device Diagnostics Ports
Diagnostic access ports on medical instruments use the CP2104-F03-GMR to expose calibration and self-test UARTs without adding firmware burden to the instrument's main MCU. The part's deterministic operation (no external crystal means no startup oscillator issues) and on-chip POR give reliable enumeration after power cycles, important for service-bay workflows. VIO operation at 1.8 V to 3.6 V lets it interface with low-voltage medical SoCs directly. Manufacturers program custom product strings via the 1024-byte OTP ROM so field-service laptops identify the diagnostic port unambiguously, and the -40C to +85C range covers storage and transport conditions per medical logistics requirements.
Empfohlen
Zusammenfassung der empfohlenen Produkte
Technische Referenzdaten für CP2104-F03-GMR – Vergleich, Designhinweise und Compliance-Informationen.
Auswahlhilfe
Vergleich mit Alternativen
| Parameter | Dieses Produkt | CP2104-F03-GM | CP2103-GM | CP2105-F01-GM | CP2110-F01-GM |
|---|---|---|---|---|---|
| Package | 24-QFN (4x4 mm) EP | 24-QFN (4x4 mm) EP - same | 24-QFN (4x4 mm) EP - same | 24-QFN (4x4 mm) EP - same | 24-QFN (4x4 mm) EP - same |
| Brand | Silicon Labs | Silicon Labs | Silicon Labs | Silicon Labs | Silicon Labs |
| UART Channels | 1 | 1 | 1 | 2 (ECI + RMI) | 1 |
| Baud Rate Range | 300 bps to 2 Mbps | 300 bps to 2 Mbps | 300 bps to 921.6 kbps | up to 2 Mbps (ECI port) | up to 921.6 kbps |
| USB Device Class | Virtual COM Port (CDC) | Virtual COM Port (CDC) | Virtual COM Port (CDC) | Virtual COM Port (CDC) | USB HID class (driverless) |
| Supply Voltage | 3 V to 3.6 V (VIO down to 1.8 V) | 3 V to 3.6 V (VIO down to 1.8 V) | 3 V to 3.6 V | 3 V to 3.6 V | 3 V to 3.6 V |
| Packaging | Tape & Reel | Tray | Tray | Tray | Tray |
Wichtigste Unterscheidungsmerkmale
- Highest FIFO in the legacy single-channel family (vs. CP2103-GM)
- Identical die, tray-vs-reel flexibility (vs. CP2104-F03-GM)
- Simpler driver model than HID-class bridges (vs. CP2110-F01-GM)
Designhinweise
Place a 4.7 uF to 10 uF ceramic capacitor within 2 mm of VDD, and another on REGIN, plus 0.1 uF high-frequency bypass caps on both rails. The exposed pad on the QFN-24 bottom must be soldered to a ground pour with at least 4-6 vias to the ground plane - it is both the primary thermal path and the return path for USB signaling. Keep the D+/D- traces 90 ohm differential impedance if possible, matched in length, and route them away from the UART lines to prevent crosstalk-induced enumeration errors.
Always pull ~RST (pin 9) high with a 4.7 kohm to 10 kohm resistor; leaving it floating causes intermittent enumeration failures caused by ambient noise. VBUS (pin 8) must be connected to the USB connector VBUS line through a divider if the bus can exceed 5.25 V, since it is a sense input. VPP (pin 16) is only for factory OTP programming - do not tie it to any rail in production boards. When using the on-chip 3.45 V regulator, remember it can power only light external loads; check current limits in the Silicon Labs datasheet before budgeting external circuits.
VIO defines the UART-side logic level, so tie it to the same rail as the connected MCU's I/O bank - connecting VIO to 3.3 V while the MCU is a 1.8 V part will overdrive the MCU inputs. For long UART runs (>30 cm), add 100 ohm series resistors near the CP2104 TXD/RST outputs to damp ringing, and consider ~RTS/~CTS flow control because the 576-byte FIFO fills quickly at 2 Mbps when the host stalls. Auto-program circuits using ~DTR and ~RTS with NPN transistor pairs should include 10 kohm base resistors to prevent latch-up during USB hot-plug transients.
Compliance-Informationen
RoHS compliant and lead-free per LCSC and Silicon Labs product listings. REACH, halogen-free, and conflict-minerals declarations should be pulled from the Silicon Labs quality portal.
