HI5767/4CBZ-T - 10-Bit 40MSPS ADC w/ VREF, SOIC-28 | Renesas
Teilenummer: HI5767/4CBZ-T ✓ Aktiv| Menge | Stückpreis | Gesamt |
|---|---|---|
| 1 | $12.85 | $12,85 |
| 10 | $11.55 | $115,50 |
| 100 | $10.18 | $1.018,00 |
| 500 | $9.1 | $4.550,00 |
| 1.000 | $8.25 | $8.250,00 |
HI5767/4CBZ-T Übersicht
An analog-to-digital converter (ADC) translates continuous analog signals into discrete digital codes; the HI5767/4CBZ-T is a 10-bit pipelined flash-style converter, sitting between 8-bit general-purpose ADCs and 12/14-bit precision converters in the data-converter taxonomy. Pipelined ADCs use cascaded low-resolution stages to achieve high sample rates with low power, making them well suited to digitising IF, video, and baseband waveforms in communications and instrumentation.
Key features include 10-bit resolution, 40 MSPS guaranteed sampling rate, internal 2.5 V voltage reference, single +5 V supply operation, low-power CMOS process, parallel CMOS-compatible digital interface, and an integrated sample-and-hold front end. The device is specified across the commercial 0C to 70C ambient range and supports 28-SOIC PCB mounting for high-density board layouts.
Architecturally, the HI5767/4CBZ-T uses a multi-stage pipeline with on-chip sample-and-hold to support full Nyquist bandwidth at the rated 40 MSPS. Its CMOS process reduces power dissipation relative to bipolar flash ADCs, while the internal reference eliminates an external reference component and the associated layout-induced drift.
Typical applications include digital video broadcast equipment, IF sampling in digital receivers, cable-modem and set-top-box downstream demodulation, CCD imaging digitisation, and general-purpose data acquisition in instrumentation. The combination of moderate resolution, high sample rate, and integrated reference is well matched to cost-sensitive consumer and industrial designs.
When designing with this device, ensure adequate bypassing (a 0.1 uF ceramic in parallel with a 10 uF tantalum) close to the supply pins, and route the analog input traces as a 50 ohm microstrip if digitising signals above 20 MHz. The internal reference does not require external load capacitance, but pin REF should be decoupled with 0.1 uF to minimise kickback noise.
This page synthesises distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone.
Drop-in-Alternativen für HI5767/4CBZ-T – gleiches Gehäuse, Pin-kompatibel. Bauteile mit anderem Gehäuse, die eine PCB-Überarbeitung erfordern, sind ausgeschlossen.
Varianten dieser Serie
Modelle derselben Serie, die drop-in-kompatibel sind mit HI5767/4CBZ-T (gleiche Bauform und Footprint) – abweichend in Package, Architecture, Input Type, Sampling Rate, Resolution.
Schnellvergleichstool – Wählen Sie Alternativbauteile für den Direktvergleich:
HI5767/4CBZ
✅ Drop-In✓ Auf Lager
$7.45 / Stück
Datenblatt ansehen →HI5767/4CB-T
✅ Drop-In✓ Auf Lager
$4.95 / Stück
Datenblatt ansehen →HI5767/6CBZ
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
HI5767/2CBZ
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
HI5746KCBZ
✅ Drop-In✓ Auf Lager
$6.8 / Stück
Datenblatt ansehen →HI5767/4CBZ-T Grenzwerte & elektrische Eigenschaften
| Auflösung | 10 bit |
| Abtastrate | 40 MSPS |
| Number of Channels | 1 |
| Architecture | Pipelined |
| Input Type | Differential, Single-Ended |
| Data Interface | Parallel (CMOS) |
| Configuration | S/H-ADC |
| Betriebsversorgungsspannung | 5 V |
| Reference Type | Internal voltage reference |
| Gehäuse / Bauform | 28-SOIC (0.295 inch, 7.50 mm width) |
| Betriebstemperatur | 0C to +70C |
| Montageart | Surface Mount |
| Packaging | Cut Tape (CT) / Reel |
| Process Technology | CMOS |
| RoHS-Status | Compliant |
| Sample-and-Hold | Integrated |
HI5767/4CBZ-T Pin-Konfiguration
| Pin 1 | DB9 — Data output bit 9 (MSB) |
| Pin 2 | DB8 — Data output bit 8 |
| Pin 3 | DB7 — Data output bit 7 |
| Pin 4 | DB6 — Data output bit 6 |
| Pin 5 | DB5 — Data output bit 5 |
| Pin 6 | DB4 — Data output bit 4 |
| Pin 7 | DB3 — Data output bit 3 |
| Pin 8 | DB2 — Data output bit 2 |
| Pin 9 | DB1 — Data output bit 1 |
| Pin 10 | DB0 — Data output bit 0 (LSB) |
| Pin 11 | DVDD — Digital supply (+5 V) |
| Pin 12 | DGND — Digital ground |
| Pin 13 | AVDD — Analog supply (+5 V) |
| Pin 14 | AGND — Analog ground |
| Pin 15 | REF — Internal reference decoupling (0.1 uF to AGND) |
| Pin 16 | NC — Not connected (per datasheet) |
| Pin 17 | IN+ — Analog positive input (differential) |
| Pin 18 | IN- — Analog negative input (differential) |
| Pin 19 | AGND — Analog ground |
| Pin 20 | AVDD — Analog supply (+5 V) |
| Pin 21 | CLK — Sample clock input |
| Pin 22 | NC — Not connected (per datasheet) |
| Pin 23 | DGND — Digital ground |
| Pin 24 | DVDD — Digital supply (+5 V) |
| Pin 25 | OE — Output enable (active low) |
| Pin 26 | NC — Not connected (per datasheet) |
| Pin 27 | NC — Not connected (per datasheet) |
| Pin 28 | NC — Not connected (per datasheet) |
Typische Anwendungen
HI5767/4CBZ-T ist geeignet für 6 Anwendungs: Digital Video Broadcast Equipment, IF Sampling in Digital Receivers, Cable Modem and Set-Top Box Downstream Demodulation, CCD Imaging Digitisation, General-Purpose Data Acquisition in Instrumentation, Industrial Control Signal Sampling.
Digital Video Broadcast Equipment
The HI5767/4CBZ-T's 10-bit resolution and 40 MSPS sample rate are well matched to digitising composite video, component YPbPr, and SDI streams in digital video broadcast equipment. The pipelined architecture provides full Nyquist-rate bandwidth at 40 MSPS, sufficient for ITU-R BT.601 standard-definition video digitisation. Placed between the analog front-end amplifier and the FPGA/ASIC video processor, the HI5767/4CBZ-T delivers 1024 discrete codes per pixel - more than adequate for broadcast-grade 8-bit video with headroom for chroma processing. Unlike 8-bit ADCs, the extra two bits reduce quantisation banding in gradient scenes. The internal 2.5 V reference eliminates drift across chassis temperature gradients, while single +5 V supply operation simplifies the broadcast-system power tree.
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IF Sampling in Digital Receivers
The HI5767/4CBZ-T excels at intermediate-frequency (IF) sampling in digital receivers where baseband signals up to 20 MHz must be digitised for downstream DSP demodulation. The 40 MSPS guaranteed sample rate exceeds the 2x Nyquist criterion for IFs below 20 MHz, while the pipelined architecture minimises pipeline latency to a few clock cycles - critical for burst-mode receivers. Per the Renesas datasheet, the integrated sample-and-hold supports full-scale input transitions at the rated clock rate without missing codes. The CMOS digital interface connects directly to a DSP or FPGA demodulator without level translation, and the 28-SOIC footprint enables compact receiver modules. Designers typically place a 50 ohm microstrip input trace plus a 0.1 uF AC-coupling cap in front of the IN+/IN- differential inputs.
Empfohlen
Cable Modem and Set-Top Box Downstream Demodulation
The HI5767/4CBZ-T is well suited to downstream channel demodulation in cable modems and set-top boxes, where QAM-modulated IF carriers between 5 MHz and 20 MHz must be digitised for symbol recovery. The 10-bit dynamic range provides ~60 dB SNR - adequate for 64-QAM constellations in clean cable plants. According to the Renesas datasheet, the integrated voltage reference simplifies the BOM by eliminating an external reference IC, lowering cost in consumer cable equipment. The 28-SOIC package fits the tight tuner/demodulator sub-board layouts typical in set-top boxes, while single +5 V supply operation aligns with the tuner subsystem power rail. The CMOS process reduces power dissipation versus bipolar flash ADCs, an advantage in sealed consumer enclosures.
Empfohlen
CCD Imaging Digitisation
The HI5767/4CBZ-T provides the bandwidth and dynamic range required for digitising charge-coupled device (CCD) sensor outputs in industrial imaging and document-scanning applications. CCD outputs swing 1 V full-scale with up to 20 MHz pixel rates; the 40 MSPS sample rate of the HI5767/4CBZ-T supports typical CCD line-scan architectures at 2x Nyquist. Per the Renesas datasheet, the integrated sample-and-hold captures fast CCD reset transitions without aperture-induced distortion, while 10-bit resolution is sufficient for the 8-bit displays common in consumer imaging. The CMOS parallel digital interface connects directly to image-processing ASICs without glue logic. Designers typically place a transimpedance amplifier and DC restore circuit between the CCD output and the ADC differential inputs.
Empfohlen
General-Purpose Data Acquisition in Instrumentation
The HI5767/4CBZ-T serves as a versatile general-purpose ADC in benchtop instrumentation, factory test equipment, and laboratory digitiser modules where moderate resolution (10-bit) and high bandwidth (40 MSPS) are required. The 28-SOIC commercial 0C to 70C temperature range suits climate-controlled lab environments, while the parallel CMOS interface simplifies connection to legacy data-acquisition FPGAs and microcontrollers. Per the Renesas datasheet, the integrated voltage reference eliminates the drift and noise of external references, an important consideration when digitising low-level analog signals. Unlike dedicated audio ADCs, the HI5767/4CBZ-T is optimised for repetitive waveform capture rather than continuous streaming. A typical application pairs it with a front-end instrumentation amplifier and an FPGA timing controller.
Empfohlen
Industrial Control Signal Sampling
The HI5767/4CBZ-T is used in industrial control systems for sampling vibration, position, and current-feedback signals in motor drives and process-control loops. The 40 MSPS sample rate provides bandwidth for closed-loop control above the audible range, while the 10-bit resolution captures encoder feedback and current-sense amplifier outputs with adequate precision. Per the Renesas datasheet, the 28-SOIC package is mechanically robust for industrial PCB assembly, and the integrated voltage reference simplifies the BOM in cost-sensitive factory-automation designs. Unlike motor-control-specific ADCs, the HI5767/4CBZ-T provides a general-purpose parallel interface compatible with industrial FPGAs. Designers typically include a 4N25 optocoupler or digital isolator between the ADC digital outputs and the downstream controller for high-voltage drive isolation.
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Zusammenfassung der empfohlenen Produkte
Technische Referenzdaten für HI5767/4CBZ-T – Vergleich, Designhinweise und Compliance-Informationen.
Auswahlhilfe
Vergleich mit Alternativen
| Parameter | Dieses Produkt | HI5767/4CBZ | HI5767/4CB | HI5767/6CBZ | HI5767/2CBZ | HI5746KCBZ |
|---|---|---|---|---|---|---|
| Brand | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics |
| Package | 28-SOIC (7.50 mm) | 28-SOIC (7.50 mm) - same | 28-SOIC (7.50 mm) - same | 28-SOIC (7.50 mm) - same | 28-SOIC (7.50 mm) - same | 28-SOIC (7.50 mm) - same |
| Resolution | 10 bit | 10 bit | 10 bit | 10 bit | 10 bit | 10 bit |
| Sampling Rate | 40 MSPS | 40 MSPS | 40 MSPS | 60 MSPS (+50%) | 20 MSPS (-50%) | 40 MSPS |
| Internal Voltage Reference | Yes | Yes | Yes | Yes | Yes | Yes |
| Architecture | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined |
| Supply Voltage | 5 V single | 5 V single | 5 V single | 5 V single | 5 V single | 5 V single |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (commercial) | 0C to +70C (commercial) | 0C to +70C (commercial) | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Data Interface | Parallel CMOS | Parallel CMOS | Parallel CMOS | Parallel CMOS | Parallel CMOS | Parallel CMOS |
| Packaging | Cut Tape / Reel | Tube | Tube | Tube | Tube | Tube |
Wichtigste Unterscheidungsmerkmale
- Integrated voltage reference eliminates external component (vs. External-reference ADCs (e.g. AD9200 without internal ref))
- Same 28-SOIC footprint across speed grades 20/40/60 MSPS (vs. HI5767/6CBZ (60 MSPS) and HI5767/2CBZ (20 MSPS))
- Single +5 V supply operation simplifies power tree (vs. AD9220 (12-bit, requires +5 V analog + 3.3 V digital))
Designhinweise
The HI5767/4CBZ-T requires a clean +5 V analog supply; per the Renesas datasheet, place a 10 uF tantalum in parallel with a 0.1 uF ceramic within 5 mm of the AVDD pin to suppress switching noise from digital rails. Separate AVDD and DVDD traces back to the regulator with ferrite beads to isolate analog and digital return currents. Estimated: at 40 MSPS the part draws ~60 mA from AVDD, so a low-noise LDO (e.g. 1A TPS7A47xx family) provides adequate headroom with margin for inrush during conversions.
Per the Renesas datasheet, route the analog IN+/IN- differential pair as a matched 50 ohm microstrip with the pair length-matched to within 0.5 mm to preserve common-mode rejection. Place the input RC anti-aliasing network within 3 mm of the ADC input pins. Keep digital output traces (DB0-DB9, CLK) routed on the opposite PCB layer with continuous ground plane beneath the analog traces to minimise digital crosstalk into the analog front-end.
Estimated: a common mistake is omitting the 0.1 uF decoupling capacitor on the REF pin - without it, internal reference kickback during conversions can inject noise into the analog input path, degrading SNR by 3-5 dB, and cause missing codes. Another pitfall is driving the CLK pin with a slow-edge signal (>2 ns rise/fall); the datasheet specifies TTL/CMOS-level clock with <1 ns rise/fall, otherwise aperture jitter degrades SNR. Do not exceed 5.5 V on AVDD/DVDD even momentarily.
Compliance-Informationen
RoHS compliant per Renesas product page. Commercial temperature grade (0C to +70C) - not AEC-Q100 qualified. For automotive designs choose an AEC-Q100 qualified alternative.