HI5767/4CBZ - 10-Bit 40MSPS ADC with Internal Vref | Renesas
MPN: HI5767/4CBZ ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $12.85 | $12.85 |
| 10 | $11.62 | $116.20 |
| 100 | $9.97 | $997.00 |
| 500 | $8.74 | $4,370.00 |
| 1,000 | $7.45 | $7,450.00 |
HI5767/4CBZ Overview
An ADC (Analog-to-Digital Converter) is a mixed-signal data conversion IC that translates continuous analog input voltages into discrete digital codes. As a pipelined flash ADC, the HI5767/4CBZ uses a multi-stage architecture to achieve high sample rates while maintaining low power consumption, occupying the middle ground between full-flash converters (faster, more power) and successive-approximation ADCs (slower, less power). Within the broader component hierarchy, this device belongs to: data converter -> ADC -> pipelined ADC -> high-speed ADC -> mixed-signal IC -> semiconductor.
Key specifications include 10-bit resolution, a 40 MSPS typical sampling rate, single +5V analog supply operation, internal 2.5V bandgap voltage reference, low-power CMOS architecture, and a parallel CMOS-compatible digital output bus. The device supports both internal and external reference modes, providing flexibility for precision and drift-critical designs. It features an input bandwidth suitable for IF undersampling and video-speed applications, and the CMOS fabrication process ensures low power dissipation (typically under 200 mW) compared to bipolar flash converters of similar speed.
Typical applications include digital video processing, high-speed instrumentation, IF sampling in communications receivers, medical imaging front-ends, radar signal processing, and digital oscilloscopes. The internal reference eliminates the need for an external reference IC in cost-sensitive designs, while the parallel output bus simplifies interface to FPGAs and ASICs. The wide SOIC-28 package footprint allows hand-solderable prototyping and rework-friendly manufacturing compared to fine-pitch QFN alternatives.
When designing with the HI5767/4CBZ, ensure the analog input is driven from a low-impedance, wideband buffer (such as a high-speed op-amp) to avoid aperture jitter and maintain SNR at the rated sampling rate. Decouple AVDD and DVDD separately to prevent digital switching noise from coupling into the analog input path. Use controlled-impedance PCB layout techniques for the analog input trace to preserve bandwidth and minimize reflections at high input frequencies.
This page synthesizes distributor pricing, drop-in Renesas/Intersil alternatives, and practical design notes not consolidated in any single datasheet.
Drop-in alternatives for HI5767/4CBZ — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with HI5767/4CBZ (same form factor and footprint) — differing in Package, Input Type, Architecture, Sampling Rate, Operating Temperature.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
HI5767/4CB-T
✅ Drop-In✓ In Stock
$4.95 / Unit
View Datasheet →HI5746KCBZ-T
✅ Drop-In✓ In Stock
$6.95 / Unit
View Datasheet →HI5766KCAZ
✅ Drop-In ⚠️ Specs Unverified✓ In Stock
$5.6 / Unit
View Datasheet →HI5714/7CB-T
✅ Drop-In ⚠️ Specs Unverified✓ In Stock
$9.2 / Unit
View Datasheet →HI5767/4CBZ Maximum Ratings & Electrical Characteristics
| Resolution | 10 bit |
| Sampling Rate | 40 MSPS (also supports 20/60 MSPS modes) |
| Number of Channels | 1 |
| Architecture | Pipelined CMOS ADC |
| Input Type | Single-ended analog input |
| Data Interface | Parallel (CMOS-compatible) |
| Voltage Reference | Internal 2.5V (external reference option supported) |
| Analog Supply Voltage | +5 V typical |
| Digital Supply Voltage | 3.3 V or 5 V |
| Operating Temperature | 0 °C to +70 °C (commercial grade) |
| Package | 28-pin SOIC (W) wide-body, 7.50 mm width |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant |
| Lead-Free | Yes |
HI5767/4CBZ Pin Configuration
| Pin 1 | AVDD — Analog +5V supply |
| Pin 2 | AIN — Analog input |
| Pin 3 | AGND — Analog ground |
| Pin 4 | REFIO — Reference I/O (internal/external select) |
| Pin 5 | REFCAP — Reference bypass capacitor |
| Pin 6 | AGND — Analog ground |
| Pin 7 | AVDD — Analog +5V supply |
| Pin 8 | NC — Not connected (per datasheet) |
| Pin 9 | D9 — Digital output bit 9 (MSB) |
| Pin 10 | D8 — Digital output bit 8 |
| Pin 11 | D7 — Digital output bit 7 |
| Pin 12 | D6 — Digital output bit 6 |
| Pin 13 | D5 — Digital output bit 5 |
| Pin 14 | D4 — Digital output bit 4 |
| Pin 15 | D3 — Digital output bit 3 |
| Pin 16 | D2 — Digital output bit 2 |
| Pin 17 | D1 — Digital output bit 1 |
| Pin 18 | D0 — Digital output bit 0 (LSB) |
| Pin 19 | DGND — Digital ground |
| Pin 20 | DVDD — Digital +3.3V or +5V supply |
| Pin 21 | CLK — Clock input |
| Pin 22 | OE — Output enable (active low) |
| Pin 23 | PD — Power down (active high) |
| Pin 24 | DGND — Digital ground |
| Pin 25 | NC — Not connected (per datasheet) |
| Pin 26 | AGND — Analog ground |
| Pin 27 | AVDD — Analog +5V supply |
| Pin 28 | AVDD — Analog +5V supply |
Typical Applications
HI5767/4CBZ is suitable for 6 applications: Digital Oscilloscope Front-End, IF Sampling in Communications Receivers, Medical Imaging Front-End, Industrial Test and Measurement, Radar Signal Processing, High-Speed Data Acquisition Systems.
Digital Oscilloscope Front-End
The HI5767/4CBZ is well-suited to mid-bandwidth digital oscilloscope and data-acquisition front-ends where 10-bit resolution at 40 MSPS is sufficient. The pipelined architecture delivers wide analog input bandwidth so the input stage can drive signals at or near the Nyquist frequency without aliasing, while the parallel CMOS digital output interfaces directly to an FPGA or ASIC capture buffer without an external serializer. The internal 2.5 V reference eliminates one analog component in the BOM, reducing both cost and PCB area in portable or handheld oscilloscope designs. Compared with bipolar flash ADCs of similar speed, the CMOS HI5767/4CBZ typically dissipates under 200 mW, simplifying thermal management in fan-less enclosures. The 28-SOIC wide-body package remains hand-solderable for prototype builds and is rework-friendly for production.
Recommended
IF Sampling in Communications Receivers
In narrowband and broadband communications receivers, the HI5767/4CBZ supports IF undersampling of intermediate-frequency signals in the 30-70 MHz range thanks to its wide analog input bandwidth. The 40 MSPS sample rate allows direct downconversion of IF carriers to baseband without a dedicated analog mixer stage, simplifying the receiver signal chain. The internal voltage reference provides stable gain calibration across temperature, critical for demodulation accuracy in cellular, land-mobile-radio, and point-to-point microwave links. The parallel 10-bit CMOS output bus feeds directly into a downstream digital downconverter (DDC) implemented in an FPGA. Pipelined CMOS architecture provides low power operation suitable for portable and battery-powered radio designs.
Recommended
Medical Imaging Front-End
The HI5767/4CBZ is used in ultrasound beamformer front-ends and other medical imaging subsystems where 10-bit dynamic range at 40 MSPS is adequate for signal capture and digitization. The pipelined architecture delivers the wide input bandwidth required to capture return echoes without distortion, and the parallel output bus enables real-time data transfer to a beamforming FPGA. The internal voltage reference simplifies factory calibration and reduces bill-of-material cost for high-volume medical equipment. The CMOS process and SOIC package meet the manufacturing requirements of FDA-regulated medical device production lines. Operating temperature range of 0-70 °C suits controlled clinical environments.
Recommended
Industrial Test and Measurement
In automated test equipment, the HI5767/4CBZ digitizes wideband sensor signals at rates up to 40 MSPS with 10-bit resolution, sufficient for vibration analysis, power-line monitoring, and high-speed control-loop feedback. The internal reference reduces part count and improves long-term stability in factory-floor installations. The 28-SOIC wide-body package withstands industrial soldering profiles and is compatible with both hand-build prototypes and high-volume SMT lines. The pipelined architecture delivers consistent latency, simplifying deterministic timing analysis in closed-loop control applications. Commercial 0-70 °C operating range suits equipment housed in temperature-controlled cabinets.
Recommended
Radar Signal Processing
In short-range radar modules such as industrial proximity sensors, automotive parking aids, and security radar, the HI5767/4CBZ digitizes wideband IF or baseband signals at 40 MSPS. The pipelined architecture provides the wide input bandwidth required to capture pulsed-Doppler returns without aliasing, and the internal reference maintains calibration across temperature cycles. The 28-SOIC wide-body package suits ruggedized PCBs using through-hole or mixed-technology construction. Parallel CMOS output connects directly to a radar processing FPGA or DSP for real-time FFT-based target detection. Low CMOS power dissipation enables fan-less module designs.
Recommended
High-Speed Data Acquisition Systems
The HI5767/4CBZ serves as the analog front-end in high-speed multi-channel data-acquisition systems for vibration, sonar, and spectral analysis. Each channel uses one HI5767/4CBZ operating at 40 MSPS with parallel digital output to a shared FPGA capture buffer. The internal voltage reference simplifies channel-to-channel gain matching in parallel configurations, and the low CMOS power dissipation allows dense PCB layouts with minimal thermal management. The 28-SOIC wide-body package is compatible with both hand-soldered prototypes and SMT production. Commercial 0-70 °C operating range suits laboratory and light-industrial installations.
Recommended
Recommended Products Summary
Engineering reference data for HI5767/4CBZ — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | HI5767/4CB-T | HI5746KCBZ-T | HI5766KCAZ | HI5714/7CB-T |
|---|---|---|---|---|---|
| Brand | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics |
| Package | 28-SOIC (W) | 28-SOIC (W) - same | 28-SOIC (W) - same | 28-SOIC (W) - same | 28-SOIC (W) - same |
| Resolution | 10 bit | 10 bit | 10 bit | 10 bit | 8 bit |
| Sampling Rate | 40 MSPS | 40 MSPS | 40 MSPS | 60 MSPS | 40 MSPS |
| Architecture | Pipelined CMOS | Pipelined CMOS | Pipelined CMOS | Pipelined CMOS | Pipelined CMOS |
| Data Interface | Parallel CMOS | Parallel CMOS | Parallel CMOS | Parallel CMOS | Parallel CMOS |
| Internal Voltage Reference | Yes (2.5V) | Yes (2.5V) | Yes (2.5V) | Yes (2.5V) | Yes (2.5V) |
| Operating Temperature | 0 °C to +70 °C | 0 °C to +70 °C | 0 °C to +70 °C | 0 °C to +70 °C | 0 °C to +70 °C |
Key Differentiators
- Internal 2.5V reference eliminates external reference IC (vs ADS830EG4 (TI, no internal reference))
- Wide-body SOIC-28 package supports hand-prototype builds (vs ADS9224RGE (QFN-16 equivalent))
- Pipelined CMOS architecture delivers sub-200 mW power (vs Bipolar flash ADC of similar speed (e.g., AD9002))
Design Notes
Place the HI5767/4CBZ analog input trace on the top layer with a continuous ground plane underneath to maintain controlled impedance (typically 50 ohm for 40 MSPS). Route the 10 parallel digital output traces with matched lengths to avoid data-bus skew - even 200 ps of mismatch can cause errors at 40 MSPS. Keep the AIN trace short and avoid vias in the analog input path; high-speed op-amp buffers should be placed within 5 mm of the AIN pin to minimize parasitic capacitance.
Decouple AVDD and DVDD separately with a 10 uF bulk capacitor and a 0.1 uF ceramic bypass capacitor placed within 2 mm of each supply pin. Use a ferrite bead or pi-filter between the analog and digital +5V rails to prevent digital switching noise from coupling into the analog input path. Add 10 nF bypass caps on every AVDD pin (4 pins total on the SOIC-28 footprint) to suppress high-frequency noise spikes. Estimated: the internal reference draws microamps and can share the analog supply rail, but separate filtering is recommended for precision designs.
Drive the analog input with a low-impedance, wideband op-amp buffer such as the AD8045 or LMH6702 to maintain SNR at the rated 40 MSPS sample rate. Source impedance above 50 ohm degrades aperture jitter performance and reduces effective ENOB. Use a 50-ohm series termination resistor at the CLK input to prevent reflections and avoid clock instability. Route the CLK signal on an inner layer with a continuous ground reference to minimize EMI emissions and avoid coupling into the analog input trace.
Do not exceed the absolute maximum analog input voltage of AVDD + 0.3 V; over-voltage on AIN can permanently damage the ESD protection diodes. Always operate the part with the PD (power down) pin tied low for normal operation - leaving it floating can cause unpredictable shutdown behavior. The internal 2.5V reference requires a 0.1 uF REFCAP bypass capacitor; omitting this capacitor causes reference instability and ADC code drift. Do not drive the digital outputs with external pull-ups above DVDD + 0.3 V; the CMOS output drivers are rated to 3.6 V maximum.
Compliance Information
RoHS compliant and lead-free per Renesas product page. Not AEC-Q100 qualified - the HI5767/4CBZ is a commercial-grade (0-70 °C) part. For automotive applications, check Renesas/Intersil AEC-Q100 qualified ADC family.
