LTC2268IUJ-12 - 12-Bit 125Msps Dual ADC, 40-QFN | Analog Devices
Teilenummer: LTC2268IUJ-12 ✓ Aktiv| Menge | Stückpreis | Gesamt |
|---|---|---|
| 1 | $23.47 | $23,47 |
| 10 | $21.5 | $215,00 |
| 100 | $18.45 | $1.845,00 |
| 500 | $16.25 | $8.125,00 |
| 1.000 | $14.5 | $14.500,00 |
LTC2268IUJ-12 Übersicht
An ADC (analog-to-digital converter) is a semiconductor device that converts continuous analog voltage signals into discrete digital codes for processing by FPGAs, ASICs, microcontrollers, or DSPs. Within the converter hierarchy, the LTC2268IUJ-12 sits at the pipelined ADC subclass, which uses multiple low-resolution flash stages to digitize high-speed signals efficiently. As a dual synchronous-sampling ADC it belongs to the data-converter family -> signal-chain IC -> mixed-signal IC -> semiconductor taxonomy. The low-power 1.8 V architecture makes it suitable for portable and thermally-constrained multi-channel systems.
Key features include ±0.3 LSB INL (typical), ±0.1 LSB DNL (typical), no missing codes over temperature, and 0.3 LSB RMS transition noise. The analog input is single-ended with an internal bypass reference and accepts differential or single-ended drive, simplifying front-end design. The output data is serialized over LVDS, reducing the FPGA/ASIC pin count to as few as 3 pins per channel. The LTC2268IUJ-12 is part of the broader LTC2268-12 family which provides pin-compatible speed grades (80 Msps / 105 Msps / 125 Msps) for design scalability.
Architecturally, the device uses a multi-stage pipelined architecture with digital error correction and an internal high-precision bandgap reference. Each stage produces a sub-ADC result, drives a DAC, and computes a residue for the next stage; final alignment produces the 12-bit code. The serial LVDS interface uses an internal PLL to derive the DDR clock from the input encode clock, eliminating the need for a separate data-clock line at sample rates up to 125 Msps.
Typical applications include multi-channel digital oscilloscopes, communications test equipment, software-defined radio (SDR) receivers, medical imaging front ends, and high-speed industrial imaging. The wide input bandwidth supports undersampling of IF/RF signals in communications systems. The LVDS output directly connects to modern FPGAs with built-in LVDS receivers (e.g., Xilinx 7-series, Intel/Altera Cyclone). For multi-board systems, the LTC2268IUJ-12 enables compact synchronized sampling without external delay-matching ICs.
When designing with this part, observe the analog input common-mode voltage requirement (0.9 V typical) to maximize SNR; AC-coupling transformers or driver op-amps (e.g., ADA4927, ADL5562) are typically used at the inputs. Provide a low-noise 1.8 V analog supply and a separate 1.8 V digital supply with a ferrite-bead isolation. Synchronize the encode clock with low-jitter sources such as a TCXO or dedicated clock generator; phase noise of the encode clock directly degrades SNR. The QFN-40 package requires thermal vias under the exposed pad to meet the rated performance over -40C to +85C.
This page synthesizes distributor pricing, drop-in pin-compatible alternatives across the LTC2268 family and competitor ADCs, and design notes that go beyond the manufacturer datasheet.
Drop-in-Alternativen für LTC2268IUJ-12 – gleiches Gehäuse, Pin-kompatibel. Bauteile mit anderem Gehäuse, die eine PCB-Überarbeitung erfordern, sind ausgeschlossen.
Varianten dieser Serie
Modelle derselben Serie, die drop-in-kompatibel sind mit LTC2268IUJ-12 (gleiche Bauform und Footprint) – abweichend in Package, Resolution, Input Type, Operating Temperature Range, RoHS Status.
Schnellvergleichstool – Wählen Sie Alternativbauteile für den Direktvergleich:
LTC2267IUJ-14
✅ Drop-In✓ Auf Lager
$31.2 / Stück
Datenblatt ansehen →LTC2267CUJ-14
✅ Drop-In ⚠️ Spezifikationen ungeprüft✓ Auf Lager
$40.99 / Stück
Datenblatt ansehen →LTC2266CUJ-12
✅ Drop-In ⚠️ Spezifikationen ungeprüft✓ Auf Lager
$11.5 / Stück
Datenblatt ansehen →LTC2265CUJ-12
✅ Drop-In ⚠️ Spezifikationen ungeprüft✓ Auf Lager
$22.4 / Stück
Datenblatt ansehen →LTC2263CUJ-12
✅ Drop-In ⚠️ Spezifikationen ungeprüft✓ Auf Lager
$19.2 / Stück
Datenblatt ansehen →LTC2268IUJ-12 Grenzwerte & elektrische Eigenschaften
| Auflösung | 12 bits |
| Number of Channels | 2 (dual, simultaneous sampling) |
| Sampling Rate (max) | 125 Msps |
| Architecture | Pipelined |
| Versorgungsspannung | 1.8 V (single) |
| Power Dissipation (per channel) | 230 mW (typ) |
| Input Type | Single-ended / differential (front-end driven) |
| Analog Input Bandwidth | 5 MHz to 170 MHz |
| Transition Noise | 0.3 LSB RMS |
| Missing Codes | None over temperature |
| Digital Output Interface | Serial LVDS (1-lane or 2-lane DDR) |
| Gehäuse | 40-pin QFN (IUJ), 6x6 mm with exposed pad |
| Montageart | Surface Mount |
| Betriebstemperaturbereich | -40C to +85C (industrial) |
| RoHS-Status | Compliant (PBF / #PBF suffix) |
| Lead-Free | Yes (Pb-free #PBF suffix) |
LTC2268IUJ-12 Pin-Konfiguration
| Pin 1 | GND — Ground |
| Pin 2 | VAIN1P — Channel 1 analog input, positive |
| Pin 3 | VAIN1N — Channel 1 analog input, negative (driven externally) |
| Pin 4 | GND — Ground |
| Pin 5 | VCM — Common-mode voltage output (~0.9 V, for input drive biasing) |
| Pin 6 | GND — Ground |
| Pin 7 | VAIN2P — Channel 2 analog input, positive |
| Pin 8 | VAIN2N — Channel 2 analog input, negative |
| Pin 9 | GND — Ground |
| Pin 10 | ENC1+ — Encode clock input, positive (LVDS/PECL) |
| Pin 11 | ENC1- — Encode clock input, negative |
| Pin 12 | GND — Ground |
| Pin 13 | ENC2+ — Encode clock input 2 (test/jitter reduction, optional) |
| Pin 14 | ENC2- — Encode clock input 2, negative |
| Pin 15 | GND — Ground |
| Pin 16 | OVDD — Digital output supply (1.8 V) |
| Pin 17 | OGND — Digital output ground |
| Pin 18 | OUT2A- — Channel 2 serial data output, negative |
| Pin 19 | OUT2A+ — Channel 2 serial data output, positive |
| Pin 20 | OGND — Digital output ground |
| Pin 21 | DCO2- — Channel 2 data clock output, negative (LVDS) |
| Pin 22 | DCO2+ — Channel 2 data clock output, positive |
| Pin 23 | OGND — Digital output ground |
| Pin 24 | OUT1A- — Channel 1 serial data output, negative |
| Pin 25 | OUT1A+ — Channel 1 serial data output, positive |
| Pin 26 | OGND — Digital output ground |
| Pin 27 | DCO1- — Channel 1 data clock output, negative |
| Pin 28 | DCO1+ — Channel 1 data clock output, positive |
| Pin 29 | OGND — Digital output ground |
| Pin 30 | MODE — Output mode select (1-lane / 2-lane) |
| Pin 31 | CS — Channel select / format control |
| Pin 32 | GND — Ground |
| Pin 33 | REF — Reference decoupling / bypass node |
| Pin 34 | GND — Ground |
| Pin 35 | REFP — Positive reference decoupling |
| Pin 36 | REFN — Negative reference decoupling |
| Pin 37 | GND — Ground |
| Pin 38 | SENSE — Reference voltage select (internal/external) |
| Pin 39 | AVDD — Analog supply (1.8 V) |
| Pin 40 | GND — Exposed pad (must be soldered to ground) |
Typische Anwendungen
LTC2268IUJ-12 ist geeignet für 7 Anwendungs: Multi-Channel Digital Oscilloscope Front End, Software-Defined Radio (SDR) Receiver, Communications Test Equipment, Medical Imaging Front End (Ultrasound / ECG), High-Speed Industrial Imaging / Machine Vision, Radar / Lidar Digitization, ATE (Automated Test Equipment) Pin Electronics.
Multi-Channel Digital Oscilloscope Front End
The LTC2268IUJ-12 digitizes two oscilloscope input channels simultaneously at up to 125 Msps, supporting a single-shot bandwidth aligned with the 170 MHz input bandwidth front end. The 71 dB SNR and 84 dB SFDR at baseband deliver ENOB close to 11.5 bits, sufficient for portable and benchtop scopes targeting 100 MHz to 200 MHz bandwidth. The serial LVDS output streams data directly to an FPGA acquisition memory, reducing board routing by ~12x versus parallel-output ADCs. Power dissipation at 230 mW per channel is low enough for 4-channel (using two devices) bench instruments without active cooling. Designers typically pair the LTC2268IUJ-12 with a dual-channel ADC driver such as the ADA4927 or ADL5562 to provide differential drive and anti-alias filtering.
Empfohlen
Software-Defined Radio (SDR) Receiver
The LTC2268IUJ-12 is well-suited to SDR baseband and IF-sampling receivers because its 5 MHz to 170 MHz input bandwidth enables direct undersampling of IF signals at up to ~250 MHz, eliminating a downconversion stage. The serial LVDS interface transmits I/Q data to a host FPGA implementing the SDR signal-processing pipeline, with 1-lane mode freeing FPGA pins for digital downconversion and filters. The 71 dB SNR floor for a 12-bit pipelined ADC supports common ham-radio, land-mobile-radio, and cellular-monitor applications. Its 230 mW per-channel power dissipation keeps total SDR-board power budgets compatible with battery-driven portable radios. Designers should pair the LTC2268IUJ-12 with a low-jitter TCXO clock source such as an SiTime SiT5155 to preserve the converter SNR.
Empfohlen
Communications Test Equipment
Communications test platforms - spectrum analyzers, vector signal analyzers, and wireless manufacturing testers - rely on wide-bandwidth ADCs for capturing wideband waveforms. The LTC2268IUJ-12's 170 MHz input bandwidth and 125 Msps sampling align with the second-Nyquist capture of up to 250 MHz IFs used in LTE, 5G NR, and Wi-Fi test receivers. The simultaneous dual-channel sampling supports dual-polarization antenna test or in-phase/quadrature digitization without skew mismatch. The serial LVDS output simplifies the board-routing between the ADC and the FPGA's DSP logic. Per the LTC2268-12 datasheet, the LVDS 2-lane DDR mode delivers two bits per encode cycle to keep FPGA serialization overhead low.
Empfohlen
Medical Imaging Front End (Ultrasound / ECG)
In ultrasound receive-front-end cards and high-channel-count ECG acquisition modules, the LTC2268IUJ-12 enables two simultaneous beams/lead channels at 125 Msps from a single 1.8 V supply, simplifying power-distribution design. The 230 mW per-channel figure is small enough that a 64-channel system (32 ADCs) draws under 15 W total, enabling fan-less patient-handling equipment. The serial LVDS output significantly reduces board trace count versus parallel-output ADCs, easing dense-array PCB layout. The 71 dB SNR floor plus 84 dB SFDR supports clinical-grade diagnostic analysis of mid-frequency ultrasound echoes. Industrial-grade -40C to +85C operation also enables portable/military medical systems.
Empfohlen
High-Speed Industrial Imaging / Machine Vision
Industrial line-scan cameras and high-frame-rate machine vision systems use dual-channel ADCs to digitize two sensor outputs simultaneously, reducing system cost and PCB area. The LTC2268IUJ-12's dual channels in a 6x6 mm QFN let designers pack two ADCs into a small camera head board, supporting resolutions up to ~2500 pixels per channel at typical sensor line rates. The 1.8 V single supply enables direct regulation from PoE (Power-over-Ethernet) derived rails through a small LDO. Industrial-grade -40C to +85C operation ensures outdoor deployments (traffic, factory-floor, railway) operate reliably without derating. Per the LTC2268-12 datasheet, the transition noise of 0.3 LSB RMS supports clean detection of low-contrast features.
Empfohlen
Radar / Lidar Digitization
Automotive and industrial radar as well as lidar receivers require moderate-bandwidth dual-channel ADCs to capture multiple antenna/mixer channels at IF frequencies. The LTC2268IUJ-12's 170 MHz input bandwidth covers the typical 40-160 MHz IF used in FMCW radar, while its 125 Msps sample rate satisfies the Nyquist criterion for IFs up to ~62.5 MHz. Its low 230 mW per-channel power helps meet the tight thermal budgets of small radar modules under a bumper or behind a windshield. The serial LVDS interface is ideal for sending multi-channel data along minimal wiring between the sensor head and the processing ECU. Designers typically pair the ADC with an FPGA-based FFT pre-processor for real-time FMCW chirp processing.
Empfohlen
ATE (Automated Test Equipment) Pin Electronics
In semiconductor ATE and board-test systems, the LTC2268IUJ-12 captures waveform digitizer channels for per-pin parametric measurements. The dual channel lets one ADC handle a stimulus-response pair, saving board space per DUT pin. The serial LVDS interface minimizes high-density backplane pin count, enabling parallel ATE architectures with hundreds of channels. The 1.8 V single supply simplifies power tree design versus older 5V/3.3V ADCs and supports modern ATE platform power budgets. Per the LTC2268-12 datasheet, no-missing-codes operation over the full industrial temperature range provides measurement confidence for production test floors without constant recalibration.
Empfohlen
Zusammenfassung der empfohlenen Produkte
Technische Referenzdaten für LTC2268IUJ-12 – Vergleich, Designhinweise und Compliance-Informationen.
Auswahlhilfe
Vergleich mit Alternativen
| Parameter | Dieses Produkt | LTC2267IUJ-14 | LTC2267CUJ-14 | LTC2266CUJ-12 | LTC2265CUJ-12 | LTC2263CUJ-12 |
|---|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 40-QFN (IUJ) 6x6 mm | 40-QFN (IUJ) 6x6 mm - same | 40-QFN (IUJ) 6x6 mm - same | 40-QFN (IUJ) 6x6 mm - same | 40-QFN (IUJ) 6x6 mm - same | 40-QFN (IUJ) 6x6 mm - same |
| Resolution | 12 bits | 14 bits | 14 bits | 12 bits | 12 bits | 12 bits |
| Maximum Sampling Rate | 125 Msps | 105 Msps | 105 Msps | 105 Msps | 80 Msps | 125 Msps (family-compatible) |
| Number of Channels | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) |
| Supply Voltage | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Operating Temperature Range | -40C to +85C (industrial) | -40C to +85C (industrial) | 0C to +70C (commercial) | 0C to +70C (commercial) | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Digital Output Interface | Serial LVDS (1-lane / 2-lane DDR) | Serial LVDS (1-lane / 2-lane DDR) | Serial LVDS (1-lane / 2-lane DDR) | Serial LVDS (1-lane / 2-lane DDR) | Serial LVDS (1-lane / 2-lane DDR) | Serial LVDS (1-lane / 2-lane DDR) |
| RoHS / Lead-Free | Yes (PBF suffix) | Yes | Yes | Yes | Yes | Yes |
Wichtigste Unterscheidungsmerkmale
- Highest sample rate in the LTC2268-12 40-QFN family (vs. LTC2267IUJ-14)
- Industrial temperature grade option (vs. LTC2266CUJ-12)
- Dual simultaneous sampling in 6x6 mm QFN (vs. Single-channel pin-compatible ADCs in larger footprints)
Designhinweise
Estimated: a 40-pin 6x6 mm QFN part dissipating ~460 mW (2 channels x 230 mW) and aiming to keep junction below 125C requires the exposed pad (EP) to be soldered to a continuous ground plane via a grid of thermal vias (typically 9 or 16 vias at 0.3 mm drill). Don't route signal traces under the EP. Keep analog inputs (VAIN1P/N, VAIN2P/N) length-matched and routed symmetrically to avoid skew between channels. Separate analog (AVDD) and digital (OVDD) supply planes connected only at a single ferrite-bead star point.
Do not drive the LTC2268IUJ-12 inputs directly from a single-ended source without AC coupling - the datasheet specifies a common-mode voltage of ~0.9 V. Use the VCM output pin to bias an input coupling transformer (e.g., Mini-Circuits ADT1-1WT) or a low-noise ADC driver such as the ADA4927. The encode clock must be a low-jitter LVDS/PECL source - SNR degrades approximately 1 dB per 5 ps of added RMS jitter; budget < 500 fs total RMS for the encode clock plus ENC distribution path.
Route the serial LVDS data pairs (OUT1A+/-, OUT2A+/-, DCO1+/-, DCO2+/-) as 100 ohm differential pairs with length matching within 0.5 mm of each other. Keep them away from the analog inputs (at least 5x the trace width) to avoid digital noise coupling. Use a continuous reference plane on an adjacent layer to control the LVDS impedance; stitch vias should be small and infrequent. Terminate the LVDS receiver side with 100 ohms differential at the FPGA's LVDS buffer per the FPGA datasheet.
Estimated: 230 mW per channel means a 2-channel configuration draws ~460 mW from the analog (AVDD) and digital (OVDD) rails combined. Use a low-noise LDO (such as LT3042 or LT1763) for the AVDD rail rather than routing a switching converter directly. Decouple both AVDD and OVDD with 0.1 uF X7R ceramics as close to the IC pins as possible (within 5 mm), plus a 10 uF bulk capacitor near the LDOs. Add a ferrite bead (e.g., BLM18AG601SN1D) between OVDD and the FPGA's LVDS supply to isolate switching noise from the digital outputs.
Compliance-Informationen
RoHS / REACH / lead-free compliance per #PBF (Pb-free) ordering suffix. Industrial-grade -40C to +85C operating range; not AEC-Q100 qualified (no automotive Q-suffix part listed in verified data).
