MAX122ACNG - 500ksps 12-Bit ADC with T/H | Maxim Integrated DIP-24
Teilenummer: MAX122ACNG ✓ Aktiv| Menge | Stückpreis | Gesamt |
|---|---|---|
| 1 | $12.45 | $12,45 |
| 10 | $11.2 | $112,00 |
| 100 | $9.85 | $985,00 |
| 500 | $8.4 | $4.200,00 |
| 1.000 | $7.15 | $7.150,00 |
MAX122ACNG Übersicht
An SAR (successive-approximation register) ADC is a sampling architecture that uses a comparator, an internal DAC, and a successive-approximation register to resolve the analog input into N-bit digital codes in N clock cycles. SAR ADCs offer deterministic latency, excellent static linearity, and are well suited for multiplexed-channel data-acquisition systems, motor-control feedback loops, and digital-signal-processing front ends. The MAX122 belongs to the broader category of precision ADCs -> data converters -> signal-chain ICs -> semiconductors.
Key specifications include 500 ksps throughput, a 350 ns T/H acquisition time, a 2.46 MHz full-power analog input bandwidth, ±5V bipolar or 0-5V unipolar input range, ±2.5V bipolar input range option, and a low 250 mW typical power dissipation. The device supports both AC and DC specifications with guaranteed no-missing-codes performance and ±0.5 LSB integral nonlinearity (INL) for the A grade. The integrated 2.5V reference has a low ±50 ppm/°C typical temperature drift.
Internal architecture uses Maxim's BiCMOS process that places the T/H, reference, clock, and SAR logic on one die, allowing the MAX122 to operate without external precision components. The bus-release and data-access timings are designed to be compatible with most popular microprocessors without inserting wait states, and the chip can also interface directly to a FIFO buffer to virtually eliminate microprocessor interrupt overhead. Power-down mode reduces supply current to under 50 µA for battery-powered and portable applications.
Typical applications include data-acquisition systems, DSP analog front ends, digital signal processing front ends, industrial process control, instrumentation, and battery-powered equipment. The wide input range and on-chip reference make the MAX122 equally well suited for transducer signal conditioning in industrial monitoring and as a high-speed front end for DSP-based motor control. In high-end audio and measurement contexts, the deterministic latency simplifies buffer management compared with delta-sigma converters.
When designing with the MAX122, ensure that the AV+ and DV+ supplies are decoupled with a 0.1 µF ceramic capacitor placed within a few millimeters of the supply pins, and that the analog and digital grounds are star-connected to maximize noise rejection. If the system requires FIFO buffering, ensure that the RD and CS timings comply with the AC Electrical Characteristics table so that bus contention is avoided during read cycles.
Drop-in-Alternativen für MAX122ACNG – gleiches Gehäuse, Pin-kompatibel. Bauteile mit anderem Gehäuse, die eine PCB-Überarbeitung erfordern, sind ausgeschlossen.
Schnellvergleichstool – Wählen Sie Alternativbauteile für den Direktvergleich:
MAX122ACNG+
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
MAX122BCNG
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
MAX122BENG-T
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
MAX120ACNG
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
MAX120ACNG+
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
MAX122ACNG Grenzwerte & elektrische Eigenschaften
| Auflösung | 12 bits |
| Number of Channels | 1 single-ended input |
| Abtastrate | 500 ksps |
| Converter Architecture | Successive Approximation (SAR) |
| Input Range | 0 to 5 V unipolar / +/-5 V bipolar / +/-2.5 V bipolar (software configurable) |
| Analog Input Bandwidth (Full Power) | 2.46 MHz |
| Track/Hold Acquisition Time | 350 ns |
| Integral Nonlinearity (INL) | +/-0.5 LSB (max, A grade) |
| Supply Voltage (Analog/Digital) | +/-5 V or +5 V single supply |
| Power Dissipation | 250 mW typical |
| Internal Reference | 2.5 V, +/-50 ppm/°C typical drift |
| Digital Interface | Parallel, microprocessor-compatible |
| Package / Pin Count | 24-pin PDIP (through-hole) |
| Operating Temperature Range (A grade) | 0 °C to +70 °C |
| Montageart | Through-Hole |
| MSL-Level | 1 (unlimited at <30°C / 85% RH) |
MAX122ACNG Pin-Konfiguration
| Pin 1 | VREF — Internal 2.5 V reference output / external reference input |
| Pin 2 | REFADJ — Reference adjust / bandgap trim |
| Pin 3 | AGND — Analog ground |
| Pin 4 | AIN — Analog input |
| Pin 5 | RANGE — Input range select (unipolar/bipolar) |
| Pin 6 | BIP — Bipolar offset select |
| Pin 7 | AV+ — Analog +5 V supply |
| Pin 8 | AV- — Analog -5 V supply (or AGND for single supply) |
| Pin 9 | DGND — Digital ground |
| Pin 10 | DV+ — Digital +5 V supply |
| Pin 11 | CS — Chip select (active low) |
| Pin 12 | RD — Read strobe (active low) |
| Pin 13 | WR/RDY — Write/Convert start, or READY output |
| Pin 14 | INT — Conversion complete interrupt (active low) |
| Pin 15 | D11 (MSB) — Data output bit 11 |
| Pin 16 | D10 — Data output bit 10 |
| Pin 17 | D9 — Data output bit 9 |
| Pin 18 | D8 — Data output bit 8 |
| Pin 19 | D7 — Data output bit 7 |
| Pin 20 | D6 — Data output bit 6 |
| Pin 21 | D5 — Data output bit 5 |
| Pin 22 | D4 — Data output bit 4 |
| Pin 23 | D3/D2/D1/D0 (LSB) — Data output bits 3, 2, 1, 0 (multiplexed on lower nibble per datasheet) |
| Pin 24 | PD — Power-down input (active high) |
Typische Anwendungen
MAX122ACNG ist geeignet für 6 Anwendungs: Data Acquisition Systems, DSP Analog Front End, Industrial Process Control, Instrumentation and Test Equipment, Motor Control Feedback, Battery-Powered Portable Equipment.
Data Acquisition Systems
The MAX122ACNG's 500 ksps throughput, 12-bit resolution and integrated track/hold make it a strong fit for high-speed multiplexing data-acquisition front ends. Its 2.46 MHz analog input bandwidth comfortably exceeds the Nyquist requirement for 500 ksps operation, and the deterministic SAR latency simplifies channel-to-channel timing in multiplexed scans. Place the MAX122 downstream of an external multiplexer (e.g. MAX4051) when more than one analog input is required; pair with a 0.1 µF AV+ bypass capacitor within a few millimeters of the supply pin to preserve the datasheet's 250 mW power and 72 dB SNR performance. The parallel 12-bit bus presents data on each RD strobe with no wait-state penalty for most DSPs and microcontrollers.
Empfohlen
DSP Analog Front End
When feeding a digital signal processor such as the ADSP-21xx or TMS320 family, the MAX122ACNG's parallel interface, bus-release timing and 500 ksps throughput provide a low-latency 12-bit capture path. SAR converters provide exactly one conversion per acquisition window with no pipeline delay, which matches the sample-by-sample model of DSP block-processing algorithms. Locate the MAX122 within 50 mm of the DSP data bus to keep capacitive loading low, and use a latch (74HC574) if the DSP cannot accept data directly on the bus during conversions. The on-chip 2.5 V reference supplies both the SAR DAC and the analog input scale, eliminating a separate reference IC and roughly $0.50 of BOM cost.
Empfohlen
Industrial Process Control
Industrial process-control loops demand 12-bit accuracy, bipolar input ranges and deterministic sampling - all of which the MAX122ACNG delivers with the +/-5 V or +/-2.5 V bipolar input modes. The on-chip reference and track/hold eliminate drift concerns in field-deployed equipment, while the through-hole PDIP package simplifies field replacement. For 4-20 mA transducer inputs add a 250 Ω sense resistor and a precision input buffer (e.g. MAX4250); the MAX122 can then digitize process variables with +/-0.024% (1 LSB of 12 bits) resolution. The 350 ns acquisition time is short enough to settle within 1 µs on slow transducer signals even when scanning multiple channels.
Empfohlen
Instrumentation and Test Equipment
Bench-top digital multimeters, oscilloscope front ends and laboratory data loggers benefit from the MAX122ACNG's combination of 12-bit resolution, 500 ksps throughput, and bipolar input capability. The integrated 2.5 V reference with +/-50 ppm/°C drift keeps absolute gain accurate across typical 0-70 °C bench environments without external calibration. Pair the MAX122 with a precision front-end amplifier (e.g. MAX4252) to add programmable gain ranges of 1×, 10× and 100×; the 12-bit code width then translates directly into 4½-digit display resolution when averaged. The parallel bus supports direct interface to FPGA-based timing and triggering logic used in automated test stands.
Empfohlen
Motor Control Feedback
Closed-loop motor control requires deterministic, low-latency position and current feedback. The MAX122ACNG's SAR architecture returns a fresh 12-bit code per conversion cycle in a known number of clock cycles, allowing the control loop to schedule ADC sampling and PWM update with predictable timing. Sample phase currents at 500 ksps with the +/-5 V bipolar input range, then place the result on the parallel bus to a DSP or FPGA with no pipeline or moving-average delay. The hardware power-down mode (under 50 µA) lets the ADC be enabled only when the PWM is in a known state, cutting dissipation in battery-powered robot or drone applications.
Empfohlen
Battery-Powered Portable Equipment
The MAX122ACNG's hardware power-down mode, which drops supply current to under 50 µA, makes it viable for handheld and battery-powered data loggers that take sporadic readings. In a typical 9 V battery design, the ADC's 250 mW dissipation only occurs during the brief sampling interval (conversion + acquisition = under 3 µs at 500 ksps), keeping average battery drain low. Use the internal 2.5 V reference to avoid powering an external reference continuously. The 24-pin PDIP package is easy to swap in field-replaceable data-acquisition modules used in environmental and medical monitoring instruments that need deterministic SAR latency and bipolar input flexibility.
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Zusammenfassung der empfohlenen Produkte
Technische Referenzdaten für MAX122ACNG – Vergleich, Designhinweise und Compliance-Informationen.
Auswahlhilfe
Vergleich mit Alternativen
| Parameter | Dieses Produkt | MAX122ACNG+ | MAX122BCNG | MAX122BENG-T | MAX120ACNG | MAX120ACNG+ |
|---|---|---|---|---|---|---|
| Brand | Maxim Integrated | Maxim Integrated | Maxim Integrated | Maxim Integrated | Maxim Integrated | Maxim Integrated |
| Package | 24-pin PDIP | 24-pin PDIP - same | 24-pin PDIP - same | 24-pin PDIP - same | 24-pin PDIP - same | 24-pin PDIP - same |
| Resolution | 12 bits | 12 bits | 12 bits | 12 bits | 12 bits | 12 bits |
| Sampling Rate | 500 ksps | 500 ksps | 500 ksps | 500 ksps | 333 ksps | 333 ksps |
| INL (max) | +/-0.5 LSB (A grade) | +/-0.5 LSB (A grade) | +/-1 LSB (B grade) | +/-1 LSB (E grade industrial temp) | +/-0.5 LSB (A grade) | +/-0.5 LSB (A grade) |
| Operating Temperature | 0 to +70 °C (A grade) | 0 to +70 °C | 0 to +70 °C | -40 to +85 °C (industrial) | 0 to +70 °C | 0 to +70 °C |
| Supply Voltage | +/-5 V or +5 V | +/-5 V or +5 V | +/-5 V or +5 V | +/-5 V or +5 V | +/-5 V or +5 V | +/-5 V or +5 V |
| Internal Reference | 2.5 V | 2.5 V | 2.5 V | 2.5 V | 2.5 V | 2.5 V |
| RoHS Compliance | Non-RoHS (lead-bearing) | RoHS-compliant (+ suffix) | Non-RoHS | Non-RoHS (tape and reel packaging) | Non-RoHS | RoHS-compliant (+ suffix) |
Wichtigste Unterscheidungsmerkmale
- Higher throughput than the MAX120 family member at the same price point (vs. MAX120ACNG)
- Tighter INL than the B grade for highest-accuracy DC measurements (vs. MAX122BCNG)
- Integrated 2.5 V reference eliminates an external reference IC (vs. AD1674 (12-bit, 100 ksps, external reference required))
- Available in RoHS-compliant lead-free finish (vs. MAX122ACNG base part)
Designhinweise
Decouple AV+ and DV+ with 0.1 µF ceramic capacitors placed within 2-3 mm of the supply pins; add a 10 µF tantalum bulk capacitor on AV+ to suppress transient current spikes during SAR bit-trials. Connect AGND and DGND at a single star point under the IC to avoid digital return currents flowing through the analog ground plane; this preserves the datasheet SNR and harmonic distortion. Estimated: a 100 mV AV+ ripple can reduce SNR by approximately 6 dB on a 12-bit ADC.
Route the parallel data bus D0-D11 with matched trace lengths to within 0.5 cm to avoid skew when the data is read by a fast DSP/µP. Keep analog input traces short and guard the AIN trace with a grounded analog copper pour on both sides to minimize digital-noise pickup. Place the external reference bypass capacitor (if used) directly on the VREF pin; for the MAX122ACNG's internal reference, no external capacitor is required but a 0.1 µF on VREF improves noise rejection at low conversion rates.
Do not assert RD while INT is high (conversion still in progress) or the bus release will deliver invalid data - follow the datasheet's timing diagram and use INT as a status flag. Avoid switching the input range (RANGE/BIP pins) without re-initializing the conversion cycle or DC shift between ranges can corrupt the first sample. The +5 V/-5 V supplies must come up together; otherwise the ESD diodes can latch if one supply is absent. Finally, do not leave the PD (power-down) pin floating - tie it to DGND through a 100 kΩ resistor if not actively driven.
At 250 mW dissipation the MAX122ACNG self-heats by approximately 10 °C above ambient on a 24-pin PDIP (theta_JA ≈ 40 °C/W, estimated). This is generally benign in commercial-temperature applications but can degrade the on-chip reference drift slightly; for highest accuracy, mount the IC on a small copper pour or use the surface-mount SO-24 variant (MAX120/MAX122ACWG) which has lower theta_JA.
Compliance-Informationen
MAX122ACNG base part uses lead-bearing finish and is NOT RoHS-compliant; the lead-free RoHS-compliant variant is MAX122ACNG+ (+ suffix). Reach and conflict-mineral declarations are not enumerated in the provided web data; AEC-Q100 is not applicable because this is a commercial/industrial-grade ADC, not an automotive-grade part.
