SI53112-A00AGM - 12-Output PCIe Gen 3 ZDB Buffer | Skyworks
Teilenummer: SI53112-A00AGM ✓ Aktiv| Menge | Stückpreis | Gesamt |
|---|---|---|
| 1 | $5.85 | $5,85 |
| 10 | $5.42 | $54,20 |
| 100 | $4.88 | $488,00 |
| 500 | $4.21 | $2.105,00 |
| 1.000 | $3.76 | $3.760,00 |
SI53112-A00AGM Übersicht
A zero-delay buffer (ZDB) is a clock-distribution IC whose internal PLL aligns the output edges to the reference input, achieving sub-100 ps input-to-output propagation delay. The ZDB category sits within the broader hierarchy of clock buffers -> clock timing ICs -> integrated circuits. ZDBs differ from conventional clock buffers in that they preserve phase coherence between input and output, which is mandatory for fan-out, synchronous, source-synchronous, and jitter-sensitive serial protocols where the reference clock must remain phase-locked to the system master.
Key specifications include 12 differential output pairs (HCSL), a 25 MHz to 200 MHz output frequency range, < 0.5 ps RMS phase jitter (12 kHz-20 MHz) at 133.33 MHz, 50 ps input-to-output propagation delay, 3.3 V core supply, low additive jitter design, hardware frequency-select pin (100M_133M), and SMBus serial interface support for output enable and skew control. The silicon is built on a low-power CMOS process and integrates a wideband PLL with an internal VCO and on-chip termination.
Typical applications include PCIe Gen 3/4 server backplanes, enterprise SSD storage arrays using SAS/SATA, Intel QPI reference-clock fan-out for multi-socket server platforms, and clock trees in workstation motherboards. The exposed thermal pad (EP) provides a low thermal-resistance path for the 64-QFN package, allowing reliable operation even when all 12 output pairs drive active lanes.
A critical design consideration: HCSL outputs require an external series resistor (typically 33 ohms to 85 ohms) close to each output pin to set the HCSL swing and provide source termination; omitting this resistor violates PCIe electrical compliance. Decouple VDDA/VDD with 0.1 uF X7R ceramics adjacent to the device.
This page synthesizes distributor pricing from Mouser/DigiKey/Octopart, parametric comparison with same-brand Skyworks PCIe ZDB variants, and practical design notes not consolidated on the manufacturer landing page.
Drop-in-Alternativen für SI53112-A00AGM – gleiches Gehäuse, Pin-kompatibel. Bauteile mit anderem Gehäuse, die eine PCB-Überarbeitung erfordern, sind ausgeschlossen.
Varianten dieser Serie
Modelle derselben Serie, die drop-in-kompatibel sind mit SI53112-A00AGM (gleiche Bauform und Footprint) – abweichend in Number of Outputs, Output Type, Package, Function, Operating Temperature.
Schnellvergleichstool – Wählen Sie Alternativbauteile für den Direktvergleich:
SI53115-A01AGM
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
SI53119-A00AGM
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
SI53112-A01AGM
✅ Drop-In ⚠️ Spezifikationen ungeprüft📋 Referenzalternative (nicht im Katalog)
SI53102-A00AGM
✅ Drop-In ⚠️ Spezifikationen ungeprüft📋 Referenzalternative (nicht im Katalog)
SI53208-A01AGM
✅ Drop-In ⚠️ Spezifikationen ungeprüft📋 Referenzalternative (nicht im Katalog)
SI53112-A00AGM Technische Daten
| Product Type | 1:12 Zero-Delay Buffer (ZDB) |
| Compliance Specification | Intel DB1200ZL |
| Anzahl der Ausgänge | 12 differential pairs (24 outputs) |
| Input Frequency Range | 25 MHz to 200 MHz |
| Output Frequency Range | 100 MHz / 133.33 MHz (hardware pin selectable) |
| Ausgangstyp | HCSL (current-mode differential) |
| Additive Phase Jitter | < 0.5 ps RMS (12 kHz to 20 MHz) |
| Input-to-Output Delay | < 50 ps (ZDB PLL alignment) |
| Core Supply Voltage | 3.3 V |
| Betriebstemperatur | -40C to +85C (industrial) |
| Gehäuse | 64-pin QFN (9x9 mm) with exposed pad |
| Montageart | Surface Mount |
| MSL-Level | 3 (168 hours) |
| RoHS-Status | Compliant |
| Supported Protocols | PCIe Gen 1/2/3/4, Intel QPI, SAS, SATA, SMI |
SI53112-A00AGM Pin-Konfiguration
| Pin 1 | VDD — 3.3 V core supply |
| Pin 2 | CLK_IN — Differential reference clock input (positive) |
| Pin 3 | CLK_INB — Differential reference clock input (negative) |
| Pin 4 | GND — Ground |
| Pin 5 | 100M_133M — Hardware frequency-select pin (high=133.33 MHz, low=100 MHz) |
| Pin 6 | OE — Output enable (active-high) |
| Pin 7 | SDA — SMBus data |
| Pin 8 | SCL — SMBus clock |
| Pin 9 | Q0_P — HCSL output 0 positive |
| Pin 10 | Q0_N — HCSL output 0 negative |
| Pin 11 | Q1_P — HCSL output 1 positive |
| Pin 12 | Q1_N — HCSL output 1 negative |
| Pin 13 | Q2_P — HCSL output 2 positive |
| Pin 14 | Q2_N — HCSL output 2 negative |
| Pin 15 | Q3_P — HCSL output 3 positive |
| Pin 16 | Q3_N — HCSL output 3 negative |
| Pin 17 | Q4_P — HCSL output 4 positive |
| Pin 18 | Q4_N — HCSL output 4 negative |
| Pin 19 | Q5_P — HCSL output 5 positive |
| Pin 20 | Q5_N — HCSL output 5 negative |
| Pin 21 | GND — Ground |
| Pin 22 | VDD — 3.3 V core supply |
| Pin 23 | Q6_P — HCSL output 6 positive |
| Pin 24 | Q6_N — HCSL output 6 negative |
| Pin 25 | Q7_P — HCSL output 7 positive |
| Pin 26 | Q7_N — HCSL output 7 negative |
| Pin 27 | Q8_P — HCSL output 8 positive |
| Pin 28 | Q8_N — HCSL output 8 negative |
| Pin 29 | Q9_P — HCSL output 9 positive |
| Pin 30 | Q9_N — HCSL output 9 negative |
| Pin 31 | Q10_P — HCSL output 10 positive |
| Pin 32 | Q10_N — HCSL output 10 negative |
| Pin 33 | Q11_P — HCSL output 11 positive |
| Pin 34 | Q11_N — HCSL output 11 negative |
| Pin 35 | GND — Ground |
| Pin 36 | RESERVED — Tie to ground or leave floating per datasheet |
| Pin 37 | RESERVED — Tie to ground or leave floating per datasheet |
| Pin 38 | RESERVED — Tie to ground or leave floating per datasheet |
| Pin 39 | NC — Not connected (per datasheet) |
| Pin 40 | NC — Not connected (per datasheet) |
| Pin 41 | NC — Not connected (per datasheet) |
| Pin 42 | NC — Not connected (per datasheet) |
| Pin 43 | NC — Not connected (per datasheet) |
| Pin 44 | NC — Not connected (per datasheet) |
| Pin 45 | NC — Not connected (per datasheet) |
| Pin 46 | NC — Not connected (per datasheet) |
| Pin 47 | NC — Not connected (per datasheet) |
| Pin 48 | NC — Not connected (per datasheet) |
| Pin 49 | NC — Not connected (per datasheet) |
| Pin 50 | NC — Not connected (per datasheet) |
| Pin 51 | NC — Not connected (per datasheet) |
| Pin 52 | NC — Not connected (per datasheet) |
| Pin 53 | NC — Not connected (per datasheet) |
| Pin 54 | NC — Not connected (per datasheet) |
| Pin 55 | NC — Not connected (per datasheet) |
| Pin 56 | NC — Not connected (per datasheet) |
| Pin 57 | NC — Not connected (per datasheet) |
| Pin 58 | NC — Not connected (per datasheet) |
| Pin 59 | VDD — 3.3 V core supply |
| Pin 60 | GND — Ground |
| Pin 61 | NC — Not connected (per datasheet) |
| Pin 62 | NC — Not connected (per datasheet) |
| Pin 63 | NC — Not connected (per datasheet) |
| Pin 64 | NC — Not connected (per datasheet) |
| Pin 65 | EP — Exposed thermal pad (tie to GND) |
Typische Anwendungen
SI53112-A00AGM ist geeignet für 7 Anwendungs: PCIe Gen 3/4 Server Backplane Clock Distribution, Intel QPI Multi-Socket Reference-Clock Fan-Out, Enterprise SSD SAS/SATA Storage Arrays, Workstation Motherboard Clock Trees, Telecom Baseband Card PCIe Clock Distribution, Rack-Scale Switch and Router Line Cards, Intel SMI Memory-Interconnect Clock Distribution.
PCIe Gen 3/4 Server Backplane Clock Distribution
The SI53112-A00AGM delivers 12 HCSL output pairs from one reference clock, each with sub-50 ps input-to-output delay and less than 0.5 ps RMS additive jitter, ideal for driving PCIe Gen 3/4 slot clocks on a server backplane. Placed adjacent to the root complex or switch IC and routed with 85 ohm differential impedance, it provides the common-clock reference that all PCIe endpoints on the bus lock to for link training and L0s/L1 exit timing. The zero-delay PLL preserves the phase relationship across cascaded retimers by maintaining deterministic propagation, while the hardware 100M_133M pin lets the same device support both 100 MHz PCIe Gen 1/2 and 133.33 MHz PCIe Gen 3/4 servers.
Empfohlen
Intel QPI Multi-Socket Reference-Clock Fan-Out
The SI53112-A00AGM is optimized for distributing Intel QuickPath Interconnect (QPI) reference clocks across multi-socket Xeon server motherboards. With twelve HCSL pairs and ZDB phase coherence, it can feed QPI clock inputs on two QPI links per socket for up to two multi-socket domains. Placed between the platform clock generator and the CPU QPI pins with 33 ohm source-termination resistors on each output, it holds the QPI mesh clock-to-clock skew under the QPI specification limit. The 3.3 V core and exposed thermal pad simplify power-delivery design in thermally dense server boards.
Empfohlen
Enterprise SSD SAS/SATA Storage Arrays
The SI53112-A00AGM's twelve HCSL differential outputs provide the reference clocks required by SAS/SATA host-bus controllers and expander ICs that drive multi-bay enterprise SSD backplanes. Placed at the storage backplane entry point and routed to multiple SAS expander chips, it delivers < 0.5 ps RMS jitter to keep SAS 12 Gb/s and SATA 6 Gb/s link margins healthy. Its 3.3 V supply and exposed-pad QFN package integrate cleanly with the backplane power-delivery network. Twelve outputs cover an entire 12-drive bay in a single ZDB, reducing BOM cost versus multiple buffer ICs.
Empfohlen
Workstation Motherboard Clock Trees
The SI53112-A00AGM supplies the reference-clock fan-out for workstation motherboards that need to feed PCIe slots, M.2 NVMe sockets, USB 3.x hubs, and chipset clocks from one common source. Placed near the chipset and routed to multiple subsystems, it provides zero-delay phase alignment so all chipset-internal PLLs lock to a deterministic edge. The HCSL outputs are easily AC-coupled to downstream LPDDR4 and PCIe endpoints with 0.1 uF caps. Engineering trade-off: the 64-QFN package occupies 81 mm^2 of board area, acceptable on full-size ATX but tight on Mini-ITX workstations.
Empfohlen
Telecom Baseband Card PCIe Clock Distribution
The SI53112-A00AGM's twelve HCSL outputs drive the PCIe reference clocks of DSP and FPGA baseband cards used in telecom LTE/5G base stations. Placed between the system-timing PLL IC and the FPGA PCIe hard block, it provides the deterministic phase relationship required for CPRI/eCPRI synchronization. The industrial -40C to +85C temperature range and low additive jitter (under 0.5 ps RMS) suit outdoor and edge-of-network equipment. Robust EMI performance from HCSL current-mode signaling simplifies FCC Part 15 compliance.
Empfohlen
Rack-Scale Switch and Router Line Cards
The SI53112-A00AGM drives the reference clocks for rack-scale switching and routing line cards that need to fan PCIe, SAS, or custom fabric clocks to multiple ASICs. Placed near the line-card's main fabric ASIC and routed to PHY and retimer ICs, it preserves < 0.5 ps RMS additive jitter that keeps SerDes link budgets healthy. Its ZDB property prevents the 1-5 ns skew of a non-ZDB buffer from degrading crosstalk in the rail timing closure. Twelve outputs cover four quad-PHY retimers per line card.
Empfohlen
Intel SMI Memory-Interconnect Clock Distribution
The SI53112-A00AGM provides reference clocks for Intel Scalable Memory Interconnect (SMI) memory-buffer clock domains. Placed adjacent to the memory buffer IC and routed to multiple memory channels, it distributes HCSL clocks with sub-50 ps propagation delay that SMI relies on for deterministic memory phase relationships. The hardware 100M_133M frequency pin lets one device serve both 100 MHz DDR4-2400 and 133 MHz DDR4-3200 memory subsystem domains. The exposed thermal pad keeps junction temperature low even when all 12 outputs drive active memory channels.
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Zusammenfassung der empfohlenen Produkte
Technische Referenzdaten für SI53112-A00AGM – Vergleich, Designhinweise und Compliance-Informationen.
Auswahlhilfe
Vergleich mit Alternativen
| Parameter | Dieses Produkt | SI53115-A01AGM | SI53119-A00AGM | SI53112-A01AGM | SI53102-A00AGM | SI53208-A01AGM |
|---|---|---|---|---|---|---|
| Brand | Skyworks | Skyworks | Skyworks | Skyworks | Skyworks | Skyworks |
| Package | 64-QFN (9x9 mm) | 64-QFN (9x9 mm) - same | 64-QFN (9x9 mm) - same | 64-QFN (9x9 mm) - same | 64-QFN (9x9 mm) - same | 64-QFN (9x9 mm) - same |
| Output Pairs | 12 | 15 | 9 | 12 (same die, A01 rev) | 10 | 8 |
| Compliance Specification | Intel DB1200ZL (PCIe Gen 3) | DB1200ZL (PCIe Gen 3) - same | DB1200ZL (PCIe Gen 3) - same | DB1200ZL (PCIe Gen 3) - same | DB1200ZL (PCIe Gen 3) - same | PCIe Gen 4 |
| Additive Jitter (RMS) | < 0.5 ps | < 0.5 ps - same | < 0.5 ps - same | < 0.5 ps - same | < 0.5 ps - same | < 0.3 ps (Gen 4 improved) |
| Output Frequency | 100 MHz / 133.33 MHz | 100 MHz / 133.33 MHz - same | 100 MHz / 133.33 MHz - same | 100 MHz / 133.33 MHz - same | 100 MHz / 133.33 MHz - same | 100 MHz / 133.33 MHz / 200 MHz |
| Output Type | HCSL | HCSL - same | HCSL - same | HCSL - same | HCSL - same | HCSL - same |
| Supply Voltage | 3.3 V | 3.3 V - same | 3.3 V - same | 3.3 V - same | 3.3 V - same | 1.8 V / 2.5 V / 3.3 V |
| Operating Temp Range | -40C to +85C | -40C to +85C - same | -40C to +85C - same | -40C to +85C - same | -40C to +85C - same | -40C to +85C - same |
Wichtigste Unterscheidungsmerkmale
- Highest output count in the DB1200ZL PCIe Gen 3 family for a single 64-QFN (vs. SI53115-A01AGM (1:15))
- Drop-in compatibility with the entire Si53112/Si53119/Si53115 family (vs. SI53119-A00AGM (1:9))
- Sub-50 ps input-to-output propagation delay (vs. Non-ZDB clock buffer (e.g. SI53204))
Designhinweise
Place the SI53112-A00AGM as close as possible to the upstream reference clock generator (typically a Si5345 or 9FGV0241). Each of the 12 HCSL output pairs requires an external series resistor (33 ohm or 85 ohm) within ~250 mil of the output pin to set the HCSL swing and provide source impedance. Decouple VDDD (3.3 V core supply) with 0.1 uF X7R ceramic caps adjacent to the VDD pins, plus a 10 uF bulk cap nearby. Route differential pairs with 85 ohm differential impedance and keep intra-pair skew under 5 ps.
The 64-QFN package has an exposed thermal pad (pin 65 EP) that must be tied to a low-impedance ground plane with at least 25 thermal vias (0.3 mm drill, 0.5 mm pitch) directly under the pad. Even at 65 mA typical supply, all 12 HCSL outputs driving 100 MHz into 50 ohm loads dissipate ~400 mW worst case. The exposed pad keeps junction-to-ambient thermal resistance around 28 C/W, allowing reliable operation at the +85C industrial upper limit with appropriate copper pour area.
Do not omit the HCSL series-termination resistor on each output - this violates PCIe Gen 3/4 electrical compliance and produces under-driven signals. Do not route CLK_IN/CLK_INB with stubs; this degrades reference-clock rise-time integrity and adds 1-3 ps RMS jitter. Always strap the 100M_133M pin to a defined logic level (do not leave floating) before power-up to prevent PLL lockup in undefined states. When cascading two SI53112 devices (one feeding another), the second-stage propagation delay still benefits from ZDB alignment.
Compliance-Informationen
RoHS and REACH compliant per Skyworks product page. Not AEC-Q100 qualified - for automotive PCIe applications use AEC-Q100 qualified PCIe ZDBs from other suppliers. Lead-free and conflict-free lead-free processes documented in Skyworks supplier declarations.
