10AS057K1F35E1HG vs 10AS057K2F35E2LG Comparación
Comparación detallada lado a lado de 10AS057K1F35E1HG por Intel y 10AS057K2F35E2LG por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | 10AS057K1F35E1HG | 10AS057K2F35E2LG |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Activo | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $1.280,00 | $3.450,00 |
| Family | Arria 10 SX SoC FPGA | Arria 10 SX SoC FPGA |
| Device Variant | 10AS057 | — |
| Logic Elements | 570,000 | 570,000 |
| Hard Processor System | Dual ARM Cortex-A9 MPCore with CoreSight | — |
| Maximum Processor Frequency | 1.5 GHz | — |
| Encapsulado | 1152-ball FC-BGA (35x35 mm) | 1152-ball FCBGA, 35 mm x 35 mm, 1.0 mm pitch |
| Speed Grade | -1 (F35) | E2 (commercial/extended) |
| Temperature Grade | Extended (E) | — |
| Embedded Memory | [DATA_NEEDED: embedded memory in Mbits] | — |
| Transceivers | Up to 24 channels | Up to 24 channels, up to 17.4 Gbps |
| Maximum Transceiver Data Rate | 17.4 Gbps | — |
| DSP Blocks | [DATA_NEEDED: DSP block count] | [DATA_NEEDED: 18x19 multiplier count] |
| Memory Interfaces | DDR4 / DDR3 with hard controllers | DDR3/DDR4 with hard PHY (HPS + FPGA) |
| HPS Peripherals | USB 2.0, Gigabit Ethernet, UART, SPI, I2C, SD/eMMC | — |
| Process Node | 20 nm | TSMC 20 nm |
| Tipo de montaje | Surface Mount (BGA) | — |
| Estado RoHS | Compliant | Compliant |
| Lead-Free | Yes | Yes |
| HPS Cores | — | Dual ARM Cortex-A9 MPCore with CoreSight |
| HPS Max Frequency | — | 1.5 GHz |
| Embedded Memory (M20K) | — | [DATA_NEEDED: M20K block count and total bits] |
| PCIe Hard IP | — | Gen3 x4 (rootport/endpoint) |
| User I/Os | — | 396 |
| Temperatura de funcionamiento | — | -40C to +100C (extended-industrial screening) |
| Configuration | — | SRAM-based, partial reconfiguration, SEU mitigation, ECC |