10AS057K1F35E1HG vs 10AS057K2F35E2LG Comparaison
Comparaison détaillée côte à côte de 10AS057K1F35E1HG par Intel et 10AS057K2F35E2LG par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | 10AS057K1F35E1HG | 10AS057K2F35E2LG |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $1 280,00 | $3 450,00 |
| Family | Arria 10 SX SoC FPGA | Arria 10 SX SoC FPGA |
| Device Variant | 10AS057 | — |
| Logic Elements | 570,000 | 570,000 |
| Hard Processor System | Dual ARM Cortex-A9 MPCore with CoreSight | — |
| Maximum Processor Frequency | 1.5 GHz | — |
| Boîtier | 1152-ball FC-BGA (35x35 mm) | 1152-ball FCBGA, 35 mm x 35 mm, 1.0 mm pitch |
| Speed Grade | -1 (F35) | E2 (commercial/extended) |
| Temperature Grade | Extended (E) | — |
| Embedded Memory | [DATA_NEEDED: embedded memory in Mbits] | — |
| Transceivers | Up to 24 channels | Up to 24 channels, up to 17.4 Gbps |
| Maximum Transceiver Data Rate | 17.4 Gbps | — |
| DSP Blocks | [DATA_NEEDED: DSP block count] | [DATA_NEEDED: 18x19 multiplier count] |
| Memory Interfaces | DDR4 / DDR3 with hard controllers | DDR3/DDR4 with hard PHY (HPS + FPGA) |
| HPS Peripherals | USB 2.0, Gigabit Ethernet, UART, SPI, I2C, SD/eMMC | — |
| Process Node | 20 nm | TSMC 20 nm |
| Type de montage | Surface Mount (BGA) | — |
| Statut RoHS | Compliant | Compliant |
| Lead-Free | Yes | Yes |
| HPS Cores | — | Dual ARM Cortex-A9 MPCore with CoreSight |
| HPS Max Frequency | — | 1.5 GHz |
| Embedded Memory (M20K) | — | [DATA_NEEDED: M20K block count and total bits] |
| PCIe Hard IP | — | Gen3 x4 (rootport/endpoint) |
| User I/Os | — | 396 |
| Température de fonctionnement | — | -40C to +100C (extended-industrial screening) |
| Configuration | — | SRAM-based, partial reconfiguration, SEU mitigation, ECC |