5CSEBA2U19C6N vs 5CSEBA2U19C7SN Comparación
Comparación detallada lado a lado de 5CSEBA2U19C6N por Intel y 5CSEBA2U19C7SN por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | 5CSEBA2U19C6N | 5CSEBA2U19C7SN |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Activo | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $74,60 | $40,33 |
| Family | Cyclone V SE SoC FPGA | Cyclone V SE FPGA SoC |
| Logic Elements | 25 K | 25,000 |
| Hard Processor System | Dual ARM Cortex-A9 MPCore with CoreSight | — |
| HPS Maximum Clock Frequency | 925 MHz | — |
| DSP Blocks | Variable-precision DSP | Variable-precision DSP |
| Encapsulado | 484-pin UBGA (19x19 mm) | 484-UBGA (19x19 mm) |
| Tipo de montaje | Surface Mount | Surface Mount (BGA) |
| Operating Temperature Grade | Commercial (other) | — |
| Memory Interfaces | DDR2, DDR3, LPDDR2 with ECC | — |
| HPS Peripherals | GbE, USB 2.0 OTG, SATA, CAN, UART, SPI, I2C, SD/SDIO/MMC | — |
| L2 Cache | 512 KB shared | — |
| L1 Cache per Core | 32 KB I-cache + 32 KB D-cache | — |
| FPGA-to-HPS Bridges | AXI-32/AXI-64, FPGA-to-SDRAM ports | — |
| Process Technology | TSMC 28 nm low-power | TSMC 28 nm low-power |
| Estado RoHS | Compliant | Compliant |
| Device Variant | — | 5CSEA2 (single-core ARM Cortex-A9) |
| Processor Hard Core | — | Single ARM Cortex-A9 MPCore with CoreSight |
| Maximum Processor Frequency | — | 800 MHz |
| User I/O Count | — | 161 (5CSEBA2 variant) |
| Speed Grade | — | C7 (commercial) |
| Temperatura de funcionamiento | — | 0C to +85C (commercial, C7 suffix) |
| Memory Blocks | — | M10K + MLAB embedded RAM |
| HPS Memory Controller | — | DDR2, DDR3, LPDDR2, LPDDR |
| Nivel MSL | — | 3 (per JEDEC J-STD-020) |