5CSEBA4U19C6N vs 5CSEBA2U19C6N Comparación
Comparación detallada lado a lado de 5CSEBA4U19C6N por Intel y 5CSEBA2U19C6N por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Intel
5CSEBA4U19C6N - Cyclone V SE SoC FPGA, 40K LE, Dual ARM Cortex-A9 | Intel
5CSEBA4U19C6N ✓ ActivoComparación de especificaciones
| Parámetro | 5CSEBA4U19C6N | 5CSEBA2U19C6N |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Activo | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $74,50 | $74,60 |
| Family | Cyclone V SE SoC FPGA | Cyclone V SE SoC FPGA |
| Logic Elements | 40,000 (40K LE) | 25 K |
| Hard Processor System (HPS) | Dual-core ARM Cortex-A9 MPCore with CoreSight | — |
| Maximum HPS Clock Frequency | 925 MHz | — |
| Encapsulado | 484-pin UFBGA / UBGA (19x19 mm) | 484-pin UBGA (19x19 mm) |
| FPGA User I/O | 161 (per Altera product page) | — |
| Process Technology | TSMC 28 nm low-power | TSMC 28 nm low-power |
| Memory Controller | Hard controller for DDR2 / DDR3 / LPDDR2 | — |
| DSP Blocks | Variable-precision DSP blocks (18x18 multipliers) | Variable-precision DSP |
| Embedded Memory | M10K memory blocks | — |
| Encryption Support | AES encryption (per LCSC listing) | — |
| Error Detection | SEU error detection and correction support | — |
| Temperatura de funcionamiento | 0C to +85C (commercial grade) | — |
| Tipo de montaje | Surface Mount (BGA) | Surface Mount |
| Estado RoHS | Compliant | Compliant |
| Hard Processor System | — | Dual ARM Cortex-A9 MPCore with CoreSight |
| HPS Maximum Clock Frequency | — | 925 MHz |
| Operating Temperature Grade | — | Commercial (other) |
| Memory Interfaces | — | DDR2, DDR3, LPDDR2 with ECC |
| HPS Peripherals | — | GbE, USB 2.0 OTG, SATA, CAN, UART, SPI, I2C, SD/SDIO/MMC |
| L2 Cache | — | 512 KB shared |
| L1 Cache per Core | — | 32 KB I-cache + 32 KB D-cache |
| FPGA-to-HPS Bridges | — | AXI-32/AXI-64, FPGA-to-SDRAM ports |