5CSEBA4U19C6N vs 5CSEBA2U19C6N Comparaison
Comparaison détaillée côte à côte de 5CSEBA4U19C6N par Intel et 5CSEBA2U19C6N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Intel
5CSEBA4U19C6N - Cyclone V SE SoC FPGA, 40K LE, Dual ARM Cortex-A9 | Intel
5CSEBA4U19C6N ✓ ActifComparaison des spécifications
| Paramètre | 5CSEBA4U19C6N | 5CSEBA2U19C6N |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $74,50 | $74,60 |
| Family | Cyclone V SE SoC FPGA | Cyclone V SE SoC FPGA |
| Logic Elements | 40,000 (40K LE) | 25 K |
| Hard Processor System (HPS) | Dual-core ARM Cortex-A9 MPCore with CoreSight | — |
| Maximum HPS Clock Frequency | 925 MHz | — |
| Boîtier | 484-pin UFBGA / UBGA (19x19 mm) | 484-pin UBGA (19x19 mm) |
| FPGA User I/O | 161 (per Altera product page) | — |
| Process Technology | TSMC 28 nm low-power | TSMC 28 nm low-power |
| Memory Controller | Hard controller for DDR2 / DDR3 / LPDDR2 | — |
| DSP Blocks | Variable-precision DSP blocks (18x18 multipliers) | Variable-precision DSP |
| Embedded Memory | M10K memory blocks | — |
| Encryption Support | AES encryption (per LCSC listing) | — |
| Error Detection | SEU error detection and correction support | — |
| Température de fonctionnement | 0C to +85C (commercial grade) | — |
| Type de montage | Surface Mount (BGA) | Surface Mount |
| Statut RoHS | Compliant | Compliant |
| Hard Processor System | — | Dual ARM Cortex-A9 MPCore with CoreSight |
| HPS Maximum Clock Frequency | — | 925 MHz |
| Operating Temperature Grade | — | Commercial (other) |
| Memory Interfaces | — | DDR2, DDR3, LPDDR2 with ECC |
| HPS Peripherals | — | GbE, USB 2.0 OTG, SATA, CAN, UART, SPI, I2C, SD/SDIO/MMC |
| L2 Cache | — | 512 KB shared |
| L1 Cache per Core | — | 32 KB I-cache + 32 KB D-cache |
| FPGA-to-HPS Bridges | — | AXI-32/AXI-64, FPGA-to-SDRAM ports |