5CSEBA6U19C6N vs 5CSEBA6U19I7N Comparación
Comparación detallada lado a lado de 5CSEBA6U19C6N por Altera y 5CSEBA6U19I7N por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Intel
5CSEBA6U19I7N - Cyclone V SE SoC FPGA, 110K LE, Dual ARM Cortex-A9 800MHz | Intel
5CSEBA6U19I7N ✓ ActivoComparación de especificaciones
| Parámetro | 5CSEBA6U19C6N | 5CSEBA6U19I7N |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Activo | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $194,15 | $142,75 |
| Manufacturer | Altera (Intel) | — |
| Series | Cyclone V SE SoC FPGA | 5CSEBA6 |
| Device Variant | 5CSEA6 (U19 package) | 5CSEA6 (U19 package, 110K LE) |
| Logic Elements | 110K | 110,000 |
| HPS Architecture | Dual ARM Cortex-A9 MPCore with CoreSight | — |
| HPS Frequency | 925 MHz | — |
| FPGA Speed Grade | -6 (industrial) | — |
| Encapsulado | 484-UBGA (UBGА, 19x19 mm) | 484-pin UBGAFBGA (UBGA-484, 19x19 mm) |
| Recuento de pines | 484 | — |
| Process Technology | TSMC 28 nm low-power | TSMC 28 nm low-power |
| User I/O | 66 (per Heisener) / configurable LVDS/LVCMOS | — |
| Hard IP Blocks | PCIe Gen2, multi-port memory controller, ARM Cortex-A9 HPS | — |
| DSP Blocks | Variable-precision DSP | 112 (18x18 multipliers) |
| Memory | Embedded M10K blocks | — |
| Temperatura de funcionamiento | -40C to +100C (industrial) | -40C to +100C (Industrial) |
| Tipo de montaje | Surface Mount (BGA) | Surface Mount (BGA) |
| Estado RoHS | Compliant (per Altera/Intel product page) | Compliant |
| Nivel MSL | 3 (per BGA package) | — |
| Family | — | Cyclone V SE SoC FPGA |
| Hard Processor System | — | Dual-core ARM Cortex-A9 MPCore |
| HPS Maximum Frequency | — | 800 MHz |
| Embedded Memory | — | 4.45 Mbits (M10K + MLAB) |
| Hard Memory Controller | — | DDR3, DDR3L, LPDDR2 |
| Transceivers | — | Up to 9 channels, 3.125 Gbps |
| PLLs | — | 6 (FPGA) + 3 (HPS) |
| User I/O Banks | — | 8 |
| Maximum User I/O | — | 288 (package-dependent) |
| Tensión de alimentación | — | Multi-rail (1.1 V core, 1.5/1.8/2.5/3.0/3.3 V I/O) |
| Configuration Modes | — | JTAG, Active Serial (AS), Passive Serial (PS), Fast Passive Parallel (FPP) |