5CSEBA6U19C6N vs 5CSEBA6U19I7N Comparaison
Comparaison détaillée côte à côte de 5CSEBA6U19C6N par Altera et 5CSEBA6U19I7N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Intel
5CSEBA6U19I7N - Cyclone V SE SoC FPGA, 110K LE, Dual ARM Cortex-A9 800MHz | Intel
5CSEBA6U19I7N ✓ ActifComparaison des spécifications
| Paramètre | 5CSEBA6U19C6N | 5CSEBA6U19I7N |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $194,15 | $142,75 |
| Manufacturer | Altera (Intel) | — |
| Series | Cyclone V SE SoC FPGA | 5CSEBA6 |
| Device Variant | 5CSEA6 (U19 package) | 5CSEA6 (U19 package, 110K LE) |
| Logic Elements | 110K | 110,000 |
| HPS Architecture | Dual ARM Cortex-A9 MPCore with CoreSight | — |
| HPS Frequency | 925 MHz | — |
| FPGA Speed Grade | -6 (industrial) | — |
| Boîtier | 484-UBGA (UBGА, 19x19 mm) | 484-pin UBGAFBGA (UBGA-484, 19x19 mm) |
| Nombre de broches | 484 | — |
| Process Technology | TSMC 28 nm low-power | TSMC 28 nm low-power |
| User I/O | 66 (per Heisener) / configurable LVDS/LVCMOS | — |
| Hard IP Blocks | PCIe Gen2, multi-port memory controller, ARM Cortex-A9 HPS | — |
| DSP Blocks | Variable-precision DSP | 112 (18x18 multipliers) |
| Memory | Embedded M10K blocks | — |
| Température de fonctionnement | -40C to +100C (industrial) | -40C to +100C (Industrial) |
| Type de montage | Surface Mount (BGA) | Surface Mount (BGA) |
| Statut RoHS | Compliant (per Altera/Intel product page) | Compliant |
| Niveau MSL | 3 (per BGA package) | — |
| Family | — | Cyclone V SE SoC FPGA |
| Hard Processor System | — | Dual-core ARM Cortex-A9 MPCore |
| HPS Maximum Frequency | — | 800 MHz |
| Embedded Memory | — | 4.45 Mbits (M10K + MLAB) |
| Hard Memory Controller | — | DDR3, DDR3L, LPDDR2 |
| Transceivers | — | Up to 9 channels, 3.125 Gbps |
| PLLs | — | 6 (FPGA) + 3 (HPS) |
| User I/O Banks | — | 8 |
| Maximum User I/O | — | 288 (package-dependent) |
| Tension d'alimentation | — | Multi-rail (1.1 V core, 1.5/1.8/2.5/3.0/3.3 V I/O) |
| Configuration Modes | — | JTAG, Active Serial (AS), Passive Serial (PS), Fast Passive Parallel (FPP) |