5M80ZM68I5N vs 5M240ZM68I5N Comparación
Comparación detallada lado a lado de 5M80ZM68I5N por Intel y 5M240ZM68I5N por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | 5M80ZM68I5N | 5M240ZM68I5N |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Activo | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $4,15 | $1,25 |
| Family | MAX V | — |
| Macro Cells | 64 | — |
| Logic Array Blocks (LABs) | 4 | — |
| Maximum Operating Frequency | 118.3 MHz | — |
| Pin-to-Pin Logic Delay (tPD) | 7.5 ns | — |
| User I/O Pins | 52 | — |
| User Flash Memory | 160 bits | — |
| Core Voltage (VCCINT) | 1.8 V (1.71 V to 1.89 V) | — |
| I/O Voltage (VCCIO) | 1.2 V / 1.5 V / 1.8 V / 2.5 V / 3.3 V | — |
| Encapsulado | 68-ball MBGA (5M80ZM68) | — |
| Tipo de montaje | Surface Mount | Surface Mount |
| Temperatura de funcionamiento | -40C to +100C (Industrial) | — |
| Programming Interface | JTAG (IEEE 1149.1) + ISP | — |
| Operating Mode | Non-volatile, instant-on | — |
| Estado RoHS | Compliant | Compliant |
| Lead-Free / Halogen-Free | Yes / Unknown | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Series | — | MAX V |
| Logic Elements | — | 240 |
| Number of Macrocells | — | 192 |
| Propagation Delay (tPD) | — | 7.5 ns |
| Configuration Memory | — | Nonvolatile Flash |
| Package Type | — | TFBGA-68 |
| Number of Terminals | — | 68 (ball) |
| Package Code | — | TFBGA |
| Form of Terminal | — | Ball |
| Package Shape | — | Square |
| Operating Temperature Grade | — | Industrial |
| JTAG Interface | — | TMS, TDI, TDO, TCK (Bank 1) |
| Programming Method | — | JTAG / in-system programmable |
| Tensión de alimentación | — | [DATA_NEEDED: VCCINT and VCCIO levels] |
| I/O Standards | — | Multiple (LVTTL, LVCMOS, SSTL, etc., per MAX V doc; PCI and 1.2 V LVCMOS excluded for JTAG pins) |
| Lead Free | — | Yes |