A3PE3000-2FG896I vs A3PE3000L-FGG896M Comparación
Comparación detallada lado a lado de A3PE3000-2FG896I por Microchip Technology y A3PE3000L-FGG896M por Microchip Technology. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Microchip Technology
A3PE3000-2FG896I - ProASIC3E FPGA 3M Gates 620 I/O | Microchip
A3PE3000-2FG896I ✓ ActivoMicrochip Technology
A3PE3000L-FGG896M - 3M-Gate Low-Power Flash FPGA | Microchip
A3PE3000L-FGG896M ✓ ActivoComparación de especificaciones
| Parámetro | A3PE3000-2FG896I | A3PE3000L-FGG896M |
|---|---|---|
| Marca | Microchip Technology | Microchip Technology |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Activo | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $195,00 | $0,00 |
| Family | ProASIC3E Flash FPGA | ProASIC3L (Flash-based FPGA) |
| System Gates | 3,000,000 | 3,000,000 |
| Logic Cells | 75,264 | 75,264 |
| Total RAM Bits | 516,096 | — |
| Number of I/Os | 620 | — |
| Supply Voltage (Core) | 1.425 V to 1.575 V (1.5 V nominal) | — |
| Speed Grade | -2 | — |
| Process Technology | 130 nm flash | 130-nm, 7-layer metal (6 copper), flash-based CMOS |
| Encapsulado / Carcasa | 896-BGA (FBGA-896, 31 x 31 mm, 1.0 mm pitch) | — |
| Tipo de montaje | Surface Mount | Surface Mount |
| Temperatura de funcionamiento | -40C to +85C ambient (+100C TJ) | 0 to 70 C |
| Configuration Memory | On-chip flash (nonvolatile, single-chip) | — |
| Packaging | Tray | — |
| Estado RoHS | Non-compliant (lead-bearing) | — |
| Manufacturer Lead Time | 8 weeks | — |
| Max System Frequency | 350 MHz (per third-party listing) | — |
| Product Status | Active | — |
| User I/Os | — | Up to 616 (620 per DigiKey listing) |
| Embedded SRAM | — | 504 kbits true dual-port |
| Core Voltage | — | 1.2 V to 1.5 V |
| Tensión de alimentación | — | 1.5 V |
| Encapsulado | — | 896-ball FBGA (FGG896), 1 mm pitch |
| Logic Family | — | CMOS |
| Configuration | — | Non-volatile flash, live-at-power-up Level 0, single-chip |
| Low-Power Feature | — | Flash*Freeze technology |
| Boundary Scan | — | IEEE 1149.1 (JTAG) |
| Input Features | — | Schmitt trigger option on single-ended inputs; weak pull-up/pull-down |