A3PE3000-2FG896I vs A3PE3000L-FGG896M Comparaison
Comparaison détaillée côte à côte de A3PE3000-2FG896I par Microchip Technology et A3PE3000L-FGG896M par Microchip Technology. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Microchip Technology
A3PE3000-2FG896I - ProASIC3E FPGA 3M Gates 620 I/O | Microchip
A3PE3000-2FG896I ✓ ActifMicrochip Technology
A3PE3000L-FGG896M - 3M-Gate Low-Power Flash FPGA | Microchip
A3PE3000L-FGG896M ✓ ActifComparaison des spécifications
| Paramètre | A3PE3000-2FG896I | A3PE3000L-FGG896M |
|---|---|---|
| Marque | Microchip Technology | Microchip Technology |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $195,00 | $0,00 |
| Family | ProASIC3E Flash FPGA | ProASIC3L (Flash-based FPGA) |
| System Gates | 3,000,000 | 3,000,000 |
| Logic Cells | 75,264 | 75,264 |
| Total RAM Bits | 516,096 | — |
| Number of I/Os | 620 | — |
| Supply Voltage (Core) | 1.425 V to 1.575 V (1.5 V nominal) | — |
| Speed Grade | -2 | — |
| Process Technology | 130 nm flash | 130-nm, 7-layer metal (6 copper), flash-based CMOS |
| Boîtier / Format | 896-BGA (FBGA-896, 31 x 31 mm, 1.0 mm pitch) | — |
| Type de montage | Surface Mount | Surface Mount |
| Température de fonctionnement | -40C to +85C ambient (+100C TJ) | 0 to 70 C |
| Configuration Memory | On-chip flash (nonvolatile, single-chip) | — |
| Packaging | Tray | — |
| Statut RoHS | Non-compliant (lead-bearing) | — |
| Manufacturer Lead Time | 8 weeks | — |
| Max System Frequency | 350 MHz (per third-party listing) | — |
| Product Status | Active | — |
| User I/Os | — | Up to 616 (620 per DigiKey listing) |
| Embedded SRAM | — | 504 kbits true dual-port |
| Core Voltage | — | 1.2 V to 1.5 V |
| Tension d'alimentation | — | 1.5 V |
| Boîtier | — | 896-ball FBGA (FGG896), 1 mm pitch |
| Logic Family | — | CMOS |
| Configuration | — | Non-volatile flash, live-at-power-up Level 0, single-chip |
| Low-Power Feature | — | Flash*Freeze technology |
| Boundary Scan | — | IEEE 1149.1 (JTAG) |
| Input Features | — | Schmitt trigger option on single-ended inputs; weak pull-up/pull-down |