A3PE3000L-1FGG896M vs A3PE3000L-FGG896M Comparación

Comparación detallada lado a lado de A3PE3000L-1FGG896M por Microchip Technology y A3PE3000L-FGG896M por Microchip Technology. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.

Microchip Technology
A3PE3000L-1FGG896M A3PE3000L-1FGG896M - 3M Gate ProASIC3L Low Power FPGA | Microchip

A3PE3000L-1FGG896M - 3M Gate ProASIC3L Low Power FPGA | Microchip

A3PE3000L-1FGG896M ✓ Activo
Microchip Technology
A3PE3000L-FGG896M A3PE3000L-FGG896M - 3M-Gate Low-Power Flash FPGA | Microchip

A3PE3000L-FGG896M - 3M-Gate Low-Power Flash FPGA | Microchip

A3PE3000L-FGG896M ✓ Activo

Comparación de especificaciones

Parámetro A3PE3000L-1FGG896M A3PE3000L-FGG896M
Marca Microchip Technology Microchip Technology
Categoría FPGA & CPLD FPGA & CPLD
Estado del ciclo de vida Activo Activo
Estado del stock In Stock In Stock
Precio unitario (USD) $432,00 $0,00
Family ProASIC3L (Flash FPGA) ProASIC3L (Flash-based FPGA)
System Gates 3000000 3,000,000
Logic Elements 35 KLEs (per Mouser listing) —
Number of I/O 620 —
Total Memory Bits (DigiKey listing) 516096 —
Core Voltage 1.2 V to 1.5 V 1.2 V to 1.5 V
Process Technology 130 nm Flash 130-nm, 7-layer metal (6 copper), flash-based CMOS
Configuration Technology Flash (nonvolatile, single-chip) —
Low Power Feature Flash*Freeze technology —
Encapsulado 896-ball FBGA 896-ball FBGA (FGG896), 1 mm pitch
Tipo de montaje Surface Mount Surface Mount
Supply Voltage - I/O as low as 1.2 V (per Microchip product page) —
Speed Grade -1 —
Temperatura de funcionamiento [DATA_NEEDED: operating temperature range] 0 to 70 C
Moisture Sensitivity [DATA_NEEDED: MSL level] —
Estado RoHS [DATA_NEEDED: RoHS status] —
Logic Cells — 75,264
User I/Os — Up to 616 (620 per DigiKey listing)
Embedded SRAM — 504 kbits true dual-port
Tensión de alimentación — 1.5 V
Logic Family — CMOS
Configuration — Non-volatile flash, live-at-power-up Level 0, single-chip
Low-Power Feature — Flash*Freeze technology
Boundary Scan — IEEE 1149.1 (JTAG)
Input Features — Schmitt trigger option on single-ended inputs; weak pull-up/pull-down

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