A3PE3000L-1FGG896M vs A3PE3000L-FGG896M Comparaison
Comparaison détaillée côte à côte de A3PE3000L-1FGG896M par Microchip Technology et A3PE3000L-FGG896M par Microchip Technology. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Microchip Technology
A3PE3000L-1FGG896M - 3M Gate ProASIC3L Low Power FPGA | Microchip
A3PE3000L-1FGG896M ✓ ActifMicrochip Technology
A3PE3000L-FGG896M - 3M-Gate Low-Power Flash FPGA | Microchip
A3PE3000L-FGG896M ✓ ActifComparaison des spécifications
| Paramètre | A3PE3000L-1FGG896M | A3PE3000L-FGG896M |
|---|---|---|
| Marque | Microchip Technology | Microchip Technology |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $432,00 | $0,00 |
| Family | ProASIC3L (Flash FPGA) | ProASIC3L (Flash-based FPGA) |
| System Gates | 3000000 | 3,000,000 |
| Logic Elements | 35 KLEs (per Mouser listing) | — |
| Number of I/O | 620 | — |
| Total Memory Bits (DigiKey listing) | 516096 | — |
| Core Voltage | 1.2 V to 1.5 V | 1.2 V to 1.5 V |
| Process Technology | 130 nm Flash | 130-nm, 7-layer metal (6 copper), flash-based CMOS |
| Configuration Technology | Flash (nonvolatile, single-chip) | — |
| Low Power Feature | Flash*Freeze technology | — |
| Boîtier | 896-ball FBGA | 896-ball FBGA (FGG896), 1 mm pitch |
| Type de montage | Surface Mount | Surface Mount |
| Supply Voltage - I/O | as low as 1.2 V (per Microchip product page) | — |
| Speed Grade | -1 | — |
| Température de fonctionnement | [DATA_NEEDED: operating temperature range] | 0 to 70 C |
| Moisture Sensitivity | [DATA_NEEDED: MSL level] | — |
| Statut RoHS | [DATA_NEEDED: RoHS status] | — |
| Logic Cells | — | 75,264 |
| User I/Os | — | Up to 616 (620 per DigiKey listing) |
| Embedded SRAM | — | 504 kbits true dual-port |
| Tension d'alimentation | — | 1.5 V |
| Logic Family | — | CMOS |
| Configuration | — | Non-volatile flash, live-at-power-up Level 0, single-chip |
| Low-Power Feature | — | Flash*Freeze technology |
| Boundary Scan | — | IEEE 1149.1 (JTAG) |
| Input Features | — | Schmitt trigger option on single-ended inputs; weak pull-up/pull-down |