A42MX16-1PQG100 vs A42MX16-PQ100 Comparación
Comparación detallada lado a lado de A42MX16-1PQG100 por Microchip Technology y A42MX16-PQ100 por Microchip Technology. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Microchip Technology
A42MX16-1PQG100 - 24K Gate MX FPGA, 83 I/O | Microchip
A42MX16-1PQG100 ✓ ActivoComparación de especificaciones
| Parámetro | A42MX16-1PQG100 | A42MX16-PQ100 |
|---|---|---|
| Marca | Microchip Technology | Microchip Technology |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Activo | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $0,00 | $1,00 |
| Family | MX (42MX) | 42MX (Actel MX) |
| System Gates | 24000 | — |
| User I/O | 83 | — |
| Program Type | One-Time Programmable (antifuse) | — |
| Tensión de alimentación | 5.0 V | 3.3 V / 5 V |
| Speed Grade | -1 | — |
| Temperature Grade | Commercial | — |
| Encapsulado | 100-BQFP (PQFP-100), gull-wing | 100-PQFP (BQFP), surface mount |
| Tipo de montaje | Surface Mount | Surface Mount |
| Terminal Form | Gull Wing | — |
| Number of Terminals | 100 | — |
| Configuration Memory | Non-volatile antifuse (no boot PROM) | — |
| JTAG Boundary Scan | Yes (IEEE 1149.1, per MX family datasheet) | — |
| Primary Use Case | Legacy PLD consolidation, ASIC alternative | — |
| Lead Free | Yes (G suffix) | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Temperatura de funcionamiento | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| Logic Gates | — | 24K gates (up to 54,000 system gates) |
| Logic Cells | — | 608 |
| System Frequency | — | 103 MHz / 172 MHz |
| Process Technology | — | 0.45 um |
| Embedded SRAM | — | 2.5 kbits configurable dual-port |
| Programming Technology | — | Antifuse (one-time programmable, non-volatile) |
| User I/O (PQ100 package) | — | 83 |
| Maximum User I/O (device) | — | Up to 202 |
| Pin Locking | — | 100% pin locking |
| Boundary Scan | — | Yes (JTAG boundary-scan register chain, TDI to TDO) |