AD7091R-2BRUZ vs LTC2313HTS8-14 Comparación
Comparación detallada lado a lado de AD7091R-2BRUZ por Analog Devices y LTC2313HTS8-14 por Analog Devices. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Analog Devices
LTC2313HTS8-14 - 14-bit 2.5Msps SAR ADC in TSOT-23-8 | Analog Devices
LTC2313HTS8-14 ✓ ActivoComparación de especificaciones
| Parámetro | AD7091R-2BRUZ | LTC2313HTS8-14 |
|---|---|---|
| Marca | Analog Devices | Analog Devices |
| Categoría | ADC/DAC | ADC/DAC |
| Estado del ciclo de vida | Activo | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $1,83 | $4,10 |
| Resolución | 12 bits | 14 bits |
| Number of Channels | 2 | — |
| Frecuencia de muestreo | 1 MSPS | — |
| Input Type | Single-ended | Pseudo-differential (IN+, IN-) |
| Tensión de alimentación | 2.7 V to 5.25 V | 3 V to 5 V (single supply, 5 V typical) |
| Power Consumption | 1.4 mW at 1 MSPS (typical) | — |
| Power-Down Current | 550 nA typical at VDD = 5.25 V, 435 nA typical at VDD = 3 V | — |
| Input Bandwidth | 1.5 MHz (track-and-hold) | — |
| Reference Type | Internal 2.5 V | — |
| Interfaz | SPI | — |
| Encapsulado | 16-lead TSSOP | TSOT-23-8 (HTS8) |
| Rango de temperatura de funcionamiento | [DATA_NEEDED: operating temperature range] | -40 °C to +125 °C (H-grade) |
| Tipo de montaje | Surface Mount | Surface Mount |
| Estado RoHS | Compliant | Compliant |
| Number of Inputs | 2 | — |
| Sample Rate | — | 2.5 Msps |
| Architecture | — | SAR (Successive Approximation Register) |
| Number of Input Channels | — | 1 (single-ended/differential) |
| Corriente de alimentación | — | 5 mA at 2.5 Msps |
| Internal Reference | — | 2.5 V nominal, 20 ppm/°C max drift |
| Serial Interface | — | SPI-compatible SCK/SDO/SDI/CSF, supports 1.8 V/2.5 V/3 V/5 V logic |
| No-Missing-Codes Performance | — | 14 bits guaranteed |
| Latency | — | 0 conversion latency |
| Nivel MSL | — | 1 (per JEDEC J-STD-020) |
| Conversion Cycles | — | 16 SCK per conversion (14-bit plus 2 dummy bits) |