AD7091R-2BRUZ vs LTC2313HTS8-14 Comparaison
Comparaison détaillée côte à côte de AD7091R-2BRUZ par Analog Devices et LTC2313HTS8-14 par Analog Devices. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Analog Devices
LTC2313HTS8-14 - 14-bit 2.5Msps SAR ADC in TSOT-23-8 | Analog Devices
LTC2313HTS8-14 ✓ ActifComparaison des spécifications
| Paramètre | AD7091R-2BRUZ | LTC2313HTS8-14 |
|---|---|---|
| Marque | Analog Devices | Analog Devices |
| Catégorie | ADC/DAC | ADC/DAC |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $1,83 | $4,10 |
| Résolution | 12 bits | 14 bits |
| Number of Channels | 2 | — |
| Fréquence d'échantillonnage | 1 MSPS | — |
| Input Type | Single-ended | Pseudo-differential (IN+, IN-) |
| Tension d'alimentation | 2.7 V to 5.25 V | 3 V to 5 V (single supply, 5 V typical) |
| Power Consumption | 1.4 mW at 1 MSPS (typical) | — |
| Power-Down Current | 550 nA typical at VDD = 5.25 V, 435 nA typical at VDD = 3 V | — |
| Input Bandwidth | 1.5 MHz (track-and-hold) | — |
| Reference Type | Internal 2.5 V | — |
| Interface | SPI | — |
| Boîtier | 16-lead TSSOP | TSOT-23-8 (HTS8) |
| Plage de température de fonctionnement | [DATA_NEEDED: operating temperature range] | -40 °C to +125 °C (H-grade) |
| Type de montage | Surface Mount | Surface Mount |
| Statut RoHS | Compliant | Compliant |
| Number of Inputs | 2 | — |
| Sample Rate | — | 2.5 Msps |
| Architecture | — | SAR (Successive Approximation Register) |
| Number of Input Channels | — | 1 (single-ended/differential) |
| Courant d'alimentation | — | 5 mA at 2.5 Msps |
| Internal Reference | — | 2.5 V nominal, 20 ppm/°C max drift |
| Serial Interface | — | SPI-compatible SCK/SDO/SDI/CSF, supports 1.8 V/2.5 V/3 V/5 V logic |
| No-Missing-Codes Performance | — | 14 bits guaranteed |
| Latency | — | 0 conversion latency |
| Niveau MSL | — | 1 (per JEDEC J-STD-020) |
| Conversion Cycles | — | 16 SCK per conversion (14-bit plus 2 dummy bits) |