AD9500WAFER vs AD9500BP Comparación
Comparación detallada lado a lado de AD9500WAFER por Analog Devices y AD9500BP por Analog Devices. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | AD9500WAFER | AD9500BP |
|---|---|---|
| Marca | Analog Devices | Analog Devices |
| Categoría | Clock & Timing | Clock & Timing |
| Estado del ciclo de vida | Activo | Unknown |
| Manufacturer | Analog Devices | — |
| Part Number | AD9500WAFER | — |
| Part Type | Digitally Programmable Delay Generator | — |
| Package / Form Factor | IC Die (bare silicon wafer form) | — |
| Programming Resolution | 8 bits digital delay programming | — |
| Analog Fine Adjust | Yes (external analog sweep / vernier input) | — |
| Trigger Input Level | CMOS / TTL compatible | — |
| Output Level | CMOS / TTL compatible | — |
| Tensión de alimentación | +5 V single supply | [DATA_NEEDED: supply voltage] |
| Supply Voltage Tolerance | [DATA_NEEDED: supply voltage tolerance] | — |
| Rango de temperatura de funcionamiento | [DATA_NEEDED: operating temperature range] | — |
| Maximum Delay Range | [DATA_NEEDED: maximum delay range in nanoseconds/microseconds] | — |
| Minimum Delay Step | [DATA_NEEDED: minimum delay step in picoseconds] | — |
| Trigger-to-Output Jitter | [DATA_NEEDED: trigger-to-output jitter] | — |
| ESD Rating (Human Body Model) | [DATA_NEEDED: HBM ESD rating - die handling only] | — |
| Package Reference (Packaged Sibling) | 24-pin ceramic Skinny DIP, 28-pin surface mount (per packaged AD9500 datasheet) | — |
| Packaged Sibling | AD9500 (ceramic DIP and SOIC packaged parts available) | — |
| Estado RoHS | [DATA_NEEDED: RoHS status of bare die] | [DATA_NEEDED: RoHS status] |
| Tipo de montaje | Die attach / wire bond / flip-chip (integrator-dependent) | — |
| Military / 883B Sibling | AD9500/883B available per MIL-STD-883 | — |
| Product Type | — | Digitally programmable delay generator |
| Delay Resolution | — | 10 ps |
| Full-Scale Delay Range | — | 10 ns |
| Programming Interface | — | 8-bit digital code |
| Input Type | — | Fully differential inputs |
| Input Logic Support | — | Single-ended or differential ECL circuits |
| Tipo de salida | — | Complementary ECL output |
| Output Feature | — | Q/R parallel output circuit |
| Trigger Inputs | — | Separate trigger input |
| Reset Inputs | — | Separate reset input |
| Power Consumption | — | Low power, mW class |
| Military Availability | — | Versions compliant with MIL-STD-883 available |
| Encapsulado | — | 28-LCC J-lead surface-mount package |
| Package Family | — | Lead-chip carrier ceramic surface-mount package |
| Ceramic DIP Variant | — | 24-pin ceramic skinny DIP, 0.3 inch package width |
| Temperatura de funcionamiento | — | [DATA_NEEDED: operating temperature range] |
| Propagation Delay | — | [DATA_NEEDED: propagation delay] |
| Jitter | — | [DATA_NEEDED: jitter] |