ADC1112D125HN-C18 vs ADC1213D080HN-C18 Comparación
Comparación detallada lado a lado de ADC1112D125HN-C18 por Renesas Electronics y ADC1213D080HN-C18 por Renesas Electronics. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Renesas Electronics
ADC1112D125HN-C18 - Dual 11-bit 125MSPS ADC, LVDS/CMOS | Renesas
ADC1112D125HN-C18 ✓ ActivoRenesas Electronics
ADC1213D080HN-C18 - 12-bit 80MSPS Dual ADC with JESD204A | Renesas
ADC1213D080HN-C18 ✓ ActivoComparación de especificaciones
| Parámetro | ADC1112D125HN-C18 | ADC1213D080HN-C18 |
|---|---|---|
| Marca | Renesas Electronics | Renesas Electronics |
| Categoría | ADC/DAC | ADC/DAC |
| Estado del ciclo de vida | Activo | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $9,48 | $21,75 |
| Resolución | 11-bit | 12 bit |
| Number of Channels | 2 (dual, simultaneous sampling) | 2 (dual, simultaneous sampling) |
| Sample Rate (Max) | 125 Msps | — |
| Analog Supply Voltage (AVDD) | 3.0 V to 3.6 V | 1.8 V |
| Digital I/O Supply (OVDD) | 1.8 V to 3.3 V | — |
| Output Interface | CMOS or LVDS DDR (selectable) | — |
| Input Type | Single-ended analog inputs (per channel) | Differential / single-ended (configurable) |
| Reference | Internal programmable (0-6 dB in 1 dB steps) or external | — |
| Control Interface | SPI (3-wire, mode configuration) | — |
| Power-Down Mode | Yes, per-channel via SPI | — |
| Encapsulado | HVQFN-64 (8x8 mm with exposed thermal pad) | 56-VFQFPN exposed pad (8x8 mm) |
| Tipo de montaje | Surface Mount | Surface Mount |
| Rango de temperatura de funcionamiento | -40 C to +85 C | -40 C to +85 C (industrial) |
| Nivel MSL | 3 (168 hours) | 3 (per JEDEC J-STD-020) |
| Estado RoHS | Compliant | Compliant |
| Sampling Rate per Channel | — | 80 MSPS |
| Architecture | — | Pipelined |
| Data Output Interface | — | JESD204A (serial, up to 3.125 Gbps lane) |
| Digital/Drive Supply Voltage (DRVDD) | — | 3.3 V |
| Input Bandwidth | — | [DATA_NEEDED: full-power input bandwidth MHz] |
| SNR | — | [DATA_NEEDED: SNR dBFS at fIN] |
| ENOB | — | [DATA_NEEDED: ENOB bits at fIN] |
| SFDR | — | [DATA_NEEDED: SFDR dBc] |
| Power Consumption | — | [DATA_NEEDED: power mW per channel at 80 MSPS] |
| Configuration Interface | — | SPI-compatible serial |
| Lead-Free | — | Yes |