ADC1112D125HN-C18 vs ADC1213D080HN-C18 Comparaison
Comparaison détaillée côte à côte de ADC1112D125HN-C18 par Renesas Electronics et ADC1213D080HN-C18 par Renesas Electronics. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Renesas Electronics
ADC1112D125HN-C18 - Dual 11-bit 125MSPS ADC, LVDS/CMOS | Renesas
ADC1112D125HN-C18 ✓ ActifRenesas Electronics
ADC1213D080HN-C18 - 12-bit 80MSPS Dual ADC with JESD204A | Renesas
ADC1213D080HN-C18 ✓ ActifComparaison des spécifications
| Paramètre | ADC1112D125HN-C18 | ADC1213D080HN-C18 |
|---|---|---|
| Marque | Renesas Electronics | Renesas Electronics |
| Catégorie | ADC/DAC | ADC/DAC |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $9,48 | $21,75 |
| Résolution | 11-bit | 12 bit |
| Number of Channels | 2 (dual, simultaneous sampling) | 2 (dual, simultaneous sampling) |
| Sample Rate (Max) | 125 Msps | — |
| Analog Supply Voltage (AVDD) | 3.0 V to 3.6 V | 1.8 V |
| Digital I/O Supply (OVDD) | 1.8 V to 3.3 V | — |
| Output Interface | CMOS or LVDS DDR (selectable) | — |
| Input Type | Single-ended analog inputs (per channel) | Differential / single-ended (configurable) |
| Reference | Internal programmable (0-6 dB in 1 dB steps) or external | — |
| Control Interface | SPI (3-wire, mode configuration) | — |
| Power-Down Mode | Yes, per-channel via SPI | — |
| Boîtier | HVQFN-64 (8x8 mm with exposed thermal pad) | 56-VFQFPN exposed pad (8x8 mm) |
| Type de montage | Surface Mount | Surface Mount |
| Plage de température de fonctionnement | -40 C to +85 C | -40 C to +85 C (industrial) |
| Niveau MSL | 3 (168 hours) | 3 (per JEDEC J-STD-020) |
| Statut RoHS | Compliant | Compliant |
| Sampling Rate per Channel | — | 80 MSPS |
| Architecture | — | Pipelined |
| Data Output Interface | — | JESD204A (serial, up to 3.125 Gbps lane) |
| Digital/Drive Supply Voltage (DRVDD) | — | 3.3 V |
| Input Bandwidth | — | [DATA_NEEDED: full-power input bandwidth MHz] |
| SNR | — | [DATA_NEEDED: SNR dBFS at fIN] |
| ENOB | — | [DATA_NEEDED: ENOB bits at fIN] |
| SFDR | — | [DATA_NEEDED: SFDR dBc] |
| Power Consumption | — | [DATA_NEEDED: power mW per channel at 80 MSPS] |
| Configuration Interface | — | SPI-compatible serial |
| Lead-Free | — | Yes |