ADC1213D125HN-C1 vs ADC1112D125HN-C18 Comparación
Comparación detallada lado a lado de ADC1213D125HN-C1 por NXP Semiconductors y ADC1112D125HN-C18 por Renesas Electronics. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
NXP Semiconductors
ADC1213D125HN-C1 - Dual 12-bit 125 Msps ADC w/ JESD204A | NXP
ADC1213D125HN-C1 ✓ ActivoRenesas Electronics
ADC1112D125HN-C18 - Dual 11-bit 125MSPS ADC, LVDS/CMOS | Renesas
ADC1112D125HN-C18 ✓ ActivoComparación de especificaciones
| Parámetro | ADC1213D125HN-C1 | ADC1112D125HN-C18 |
|---|---|---|
| Marca | NXP Semiconductors | Renesas Electronics |
| Categoría | ADC/DAC | ADC/DAC |
| Estado del ciclo de vida | Activo | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $31,20 | $9,48 |
| Number of Bits | 12 bit | — |
| Number of Channels | 2 (dual) | 2 (dual, simultaneous sampling) |
| Frecuencia de muestreo | 125 Msps (also 65/80/105 Msps modes) | — |
| Data Interface | Serial JESD204A (subclass 0) | — |
| JESD204A Lanes | 2 lanes, up to 1.25 Gbps per lane | — |
| Architecture | Pipelined with per-channel sample-and-hold | — |
| Analog Supply Voltage | 1.8 V | — |
| Digital Supply Voltage | 1.8 V | — |
| Input Type | Differential analog inputs (per channel) | Single-ended analog inputs (per channel) |
| Encapsulado | 56-HVQFN exposed pad (8x8 mm) | HVQFN-64 (8x8 mm with exposed thermal pad) |
| Tipo de montaje | Surface Mount | Surface Mount |
| Rango de temperatura de funcionamiento | [DATA_NEEDED: operating temperature range] | -40 C to +85 C |
| Internal Voltage Reference | Yes (on-chip) | — |
| Per-Channel Gain Adjustment | Yes (programmable) | — |
| Power Consumption | [DATA_NEEDED: typical power at 125 Msps] | — |
| Estado RoHS | Compliant | Compliant |
| Resolución | — | 11-bit |
| Sample Rate (Max) | — | 125 Msps |
| Analog Supply Voltage (AVDD) | — | 3.0 V to 3.6 V |
| Digital I/O Supply (OVDD) | — | 1.8 V to 3.3 V |
| Output Interface | — | CMOS or LVDS DDR (selectable) |
| Reference | — | Internal programmable (0-6 dB in 1 dB steps) or external |
| Control Interface | — | SPI (3-wire, mode configuration) |
| Power-Down Mode | — | Yes, per-channel via SPI |
| Nivel MSL | — | 3 (168 hours) |