CDK2307AILP64 vs CDK2308AILP64 Comparación
Comparación detallada lado a lado de CDK2307AILP64 por Cadeka y CDK2308AILP64 por MaxLinear. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | CDK2307AILP64 | CDK2308AILP64 |
|---|---|---|
| Marca | Cadeka | MaxLinear |
| Categoría | ADC/DAC | ADC/DAC |
| Estado del ciclo de vida | Activo | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $7,10 | $7,20 |
| Manufacturer | Cadeka Microcircuits (MaxLinear) | Exar (MaxLinear) |
| Part Number | CDK2307AILP64 | CDK2308AILP64 |
| Description | Dual 12/13-bit 20/40/65/80 MSPS Analog-to-Digital Converter | — |
| Resolución | 13 bit (12-bit option via CDK2308 family) | 10 bit |
| Sampling Rate (this variant) | 20 MSPS | — |
| Sampling Rate (family max) | 80 MSPS (CDK2307AILP64 = 20 MSPS grade) | — |
| Number of Channels | 2 (dual, simultaneous sampling) | 2 (Dual) |
| Input Type | Single-ended analog input | Differential / Single-ended analog |
| Output Interface | Parallel CMOS | — |
| Core Supply Voltage | 1.8 V | — |
| I/O Supply Voltage | 1.7 V to 3.6 V | — |
| Power Dissipation | 30 mW at 20 MSPS; 55/85/102 mW at 40/65/80 MSPS | [DATA_NEEDED: power in mW] |
| Reference | Internal (bandgap, integrated) | — |
| Encapsulado | 64-pin QFN (LP64) with exposed pad, 9x9 mm | 64-pin QFN (LP) 9x9 mm with exposed pad |
| Tipo de montaje | Surface Mount | Surface Mount |
| Temperatura de funcionamiento | -40C to +85C (industrial) [DATA_NEEDED: exact temp grade] | — |
| Pin Compatibility | Pin-compatible with CDK2308 family (12-bit variant) | — |
| Estado RoHS | Compliant | Compliant (per distributor listings) |
| Sampling Rate (Grade ILP64) | — | 20 MSPS |
| Family Maximum Sampling Rate | — | 80 MSPS (per family datasheet) |
| Architecture | — | Pipelined |
| Analog Supply Voltage | — | +3.3 V |
| Digital Supply Voltage | — | +3.3 V |
| Data Interface | — | Parallel CMOS / TTL |
| Rango de temperatura de funcionamiento | — | -40C to +85C (industrial) |
| Internal Reference | — | Yes (bandgap) |
| Input Bandwidth | — | [DATA_NEEDED: input bandwidth MHz] |
| INL (Integral Non-Linearity) | — | [DATA_NEEDED: INL in LSB] |
| DNL (Differential Non-Linearity) | — | [DATA_NEEDED: DNL in LSB] |
| SNR | — | [DATA_NEEDED: SNR dBFS] |