CDK2307AILP64 vs CDK2308AILP64 Comparaison
Comparaison détaillée côte à côte de CDK2307AILP64 par Cadeka et CDK2308AILP64 par MaxLinear. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | CDK2307AILP64 | CDK2308AILP64 |
|---|---|---|
| Marque | Cadeka | MaxLinear |
| Catégorie | ADC/DAC | ADC/DAC |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $7,10 | $7,20 |
| Manufacturer | Cadeka Microcircuits (MaxLinear) | Exar (MaxLinear) |
| Part Number | CDK2307AILP64 | CDK2308AILP64 |
| Description | Dual 12/13-bit 20/40/65/80 MSPS Analog-to-Digital Converter | — |
| Résolution | 13 bit (12-bit option via CDK2308 family) | 10 bit |
| Sampling Rate (this variant) | 20 MSPS | — |
| Sampling Rate (family max) | 80 MSPS (CDK2307AILP64 = 20 MSPS grade) | — |
| Number of Channels | 2 (dual, simultaneous sampling) | 2 (Dual) |
| Input Type | Single-ended analog input | Differential / Single-ended analog |
| Output Interface | Parallel CMOS | — |
| Core Supply Voltage | 1.8 V | — |
| I/O Supply Voltage | 1.7 V to 3.6 V | — |
| Power Dissipation | 30 mW at 20 MSPS; 55/85/102 mW at 40/65/80 MSPS | [DATA_NEEDED: power in mW] |
| Reference | Internal (bandgap, integrated) | — |
| Boîtier | 64-pin QFN (LP64) with exposed pad, 9x9 mm | 64-pin QFN (LP) 9x9 mm with exposed pad |
| Type de montage | Surface Mount | Surface Mount |
| Température de fonctionnement | -40C to +85C (industrial) [DATA_NEEDED: exact temp grade] | — |
| Pin Compatibility | Pin-compatible with CDK2308 family (12-bit variant) | — |
| Statut RoHS | Compliant | Compliant (per distributor listings) |
| Sampling Rate (Grade ILP64) | — | 20 MSPS |
| Family Maximum Sampling Rate | — | 80 MSPS (per family datasheet) |
| Architecture | — | Pipelined |
| Analog Supply Voltage | — | +3.3 V |
| Digital Supply Voltage | — | +3.3 V |
| Data Interface | — | Parallel CMOS / TTL |
| Plage de température de fonctionnement | — | -40C to +85C (industrial) |
| Internal Reference | — | Yes (bandgap) |
| Input Bandwidth | — | [DATA_NEEDED: input bandwidth MHz] |
| INL (Integral Non-Linearity) | — | [DATA_NEEDED: INL in LSB] |
| DNL (Differential Non-Linearity) | — | [DATA_NEEDED: DNL in LSB] |
| SNR | — | [DATA_NEEDED: SNR dBFS] |