EP1810GC-35AB vs EP1810GC-35 Comparación
Comparación detallada lado a lado de EP1810GC-35AB por Altera y EP1810GC-35 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP1810GC-35AB | EP1810GC-35 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Última compra |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $9,95 | $177,12 |
| Product Family | Classic EPLD | — |
| Technology | CMOS EPROM | CMOS, UV-erasable EPROM cells |
| Number of Macrocells | 48 | — |
| Number of Usable Gates | 1200 | — |
| Maximum Inputs | 64 | 64 |
| Maximum Outputs | 48 | 48 |
| Number of I/O Pins | 48 | — |
| Dedicated Input Pins | 12 | — |
| Propagation Delay (tPD) | 35 ns | — |
| Maximum Toggle Frequency | 62.5 MHz | — |
| Supply Voltage (VCC) | 5 V | — |
| Package Type | Pin Grid Array (PGA), ceramic | — |
| Temperatura de funcionamiento | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| Programming Method | UV-erasable EPROM, in-system via JTAG-like interface | UV erasure + EPROM programming |
| Estado RoHS | unknown | Not applicable (legacy ceramic package) |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Logic Family | — | Altera Classic EPLD |
| Encapsulado | — | CPGA-68 (Ceramic Pin Grid Array, 68-pin) |
| Número de pines | — | 68 |
| Propagation Delay (tpd max) | — | 40 ns |
| Macrocells | — | 16 |
| I/O Standard | — | TTL-compatible |
| Tensión de alimentación | — | [DATA_NEEDED: VCC range] |
| Tipo de montaje | — | Through Hole |
| Lead-Free Status | — | Not applicable |
| Manufacturer (current source) | — | Rochester Electronics (authorized Altera EPLD partner) |
| Original Manufacturer | — | Altera Corporation (now Intel FPGA) |