EP1810GC-35AB vs EP1810JC35 Comparación
Comparación detallada lado a lado de EP1810GC-35AB por Altera y EP1810JC35 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP1810GC-35AB | EP1810JC35 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $9,95 | $9,75 |
| Product Family | Classic EPLD | — |
| Technology | CMOS EPROM | — |
| Number of Macrocells | 48 | — |
| Number of Usable Gates | 1200 | — |
| Maximum Inputs | 64 | — |
| Maximum Outputs | 48 | — |
| Number of I/O Pins | 48 | — |
| Dedicated Input Pins | 12 | — |
| Propagation Delay (tPD) | 35 ns | 35 ns |
| Maximum Toggle Frequency | 62.5 MHz | — |
| Supply Voltage (VCC) | 5 V | — |
| Package Type | Pin Grid Array (PGA), ceramic | — |
| Temperatura de funcionamiento | [DATA_NEEDED: operating temperature range] | 0 C to +70 C (Commercial) |
| Programming Method | UV-erasable EPROM, in-system via JTAG-like interface | — |
| Estado RoHS | unknown | [DATA_NEEDED: RoHS compliance for EP1810JC35] |
| Family | — | Altera Classic EPLD |
| Product Type | — | UV-erasable / OTP Complex PLD (EPLD) |
| Macrocells | — | 48 |
| Logic Gates (typ.) | — | [DATA_NEEDED: logic gates count] |
| Maximum User I/O Pins | — | [DATA_NEEDED: user I/O count for PLCC-68] |
| Frecuencia de reloj máxima | — | 40 MHz |
| Supply Voltage (VCC max) | — | 5.25 V |
| Supply Voltage (VCC min) | — | [DATA_NEEDED: VCC minimum] |
| Process Technology | — | CMOS EPROM cell |
| Encapsulado | — | PLCC-68 (J-lead, ceramic) |
| Package Code | — | QCCJ |
| Terminal Form | — | J-BEND |
| Number of Terminals | — | 68 |
| Programming | — | UV-erase (windowed) or OTP |
| Development Tool | — | Altera MAX+plus II / A+plus |