EP1810JC-35 vs EP1810JI-35 Comparación
Comparación detallada lado a lado de EP1810JC-35 por Intel y EP1810JI-35 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP1810JC-35 | EP1810JI-35 |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $5,48 | $18,60 |
| Device Family | Classic EPLD (EP1810) | Classic EPLD |
| Device Type | UV-Erasable Complex PLD (UV PLD / CPLD) | — |
| Number of Macrocells | 48 | — |
| Propagation Delay (tpd) | 35 ns (max) | — |
| Frecuencia de reloj máxima | [DATA_NEEDED: fmax for this speed grade] | — |
| Process Technology | CMOS | CMOS EPROM (UV-erasable) |
| Supply Voltage (Vcc) | 5 V (nominal) | — |
| Maximum Supply Voltage | 5.25 V (per distributor listing) | — |
| Package Type | CQCC-68 (Ceramic J-Lead Chip Carrier, QCCJ) | — |
| Number of Terminals | 68 | — |
| Terminal Form | J-Bend | — |
| Rango de temperatura de funcionamiento | 0°C to 70°C (Commercial) | — |
| Temperature Grade | Commercial | — |
| Erasure Method | UV (quartz-windowed ceramic package) | — |
| Estado RoHS | Compliant (per Altera listing) | [DATA_NEEDED: RoHS compliance for ceramic windowed JLCC] |
| Lead-Free Status | Lead-free (per distributor listing) | — |
| Tipo de montaje | Surface Mount (J-Lead) | Through-Hole (J-lead) |
| Logic Architecture | Programmable AND/OR array with macrocell outputs | — |
| Macrocells | — | 48 |
| Logic Array Blocks | — | 8 LABs of 16 macrocells |
| Dedicated Inputs | — | 48 |
| Pin-to-Pin Propagation Delay (tPD) | — | 35 ns |
| Speed Grade | — | -35 |
| Encapsulado | — | 28-pin JLCC (J-leaded ceramic, windowed) |
| Temperatura de funcionamiento | — | -40C to +85C (Industrial) |
| Tensión de alimentación | — | 5 V (typical classic EPLD) |
| Programmability | — | UV-erase, windowed for lab reprogram |
| Nivel MSL | — | [DATA_NEEDED: MSL rating] |
| Programming Interface | — | JEDEC fuse file via legacy programmer |