EP1810JC-35 vs EP1810JI-35 Comparaison
Comparaison détaillée côte à côte de EP1810JC-35 par Intel et EP1810JI-35 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP1810JC-35 | EP1810JI-35 |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $5,48 | $18,60 |
| Device Family | Classic EPLD (EP1810) | Classic EPLD |
| Device Type | UV-Erasable Complex PLD (UV PLD / CPLD) | — |
| Number of Macrocells | 48 | — |
| Propagation Delay (tpd) | 35 ns (max) | — |
| Fréquence d'horloge maximale | [DATA_NEEDED: fmax for this speed grade] | — |
| Process Technology | CMOS | CMOS EPROM (UV-erasable) |
| Supply Voltage (Vcc) | 5 V (nominal) | — |
| Maximum Supply Voltage | 5.25 V (per distributor listing) | — |
| Package Type | CQCC-68 (Ceramic J-Lead Chip Carrier, QCCJ) | — |
| Number of Terminals | 68 | — |
| Terminal Form | J-Bend | — |
| Plage de température de fonctionnement | 0°C to 70°C (Commercial) | — |
| Temperature Grade | Commercial | — |
| Erasure Method | UV (quartz-windowed ceramic package) | — |
| Statut RoHS | Compliant (per Altera listing) | [DATA_NEEDED: RoHS compliance for ceramic windowed JLCC] |
| Lead-Free Status | Lead-free (per distributor listing) | — |
| Type de montage | Surface Mount (J-Lead) | Through-Hole (J-lead) |
| Logic Architecture | Programmable AND/OR array with macrocell outputs | — |
| Macrocells | — | 48 |
| Logic Array Blocks | — | 8 LABs of 16 macrocells |
| Dedicated Inputs | — | 48 |
| Pin-to-Pin Propagation Delay (tPD) | — | 35 ns |
| Speed Grade | — | -35 |
| Boîtier | — | 28-pin JLCC (J-leaded ceramic, windowed) |
| Température de fonctionnement | — | -40C to +85C (Industrial) |
| Tension d'alimentation | — | 5 V (typical classic EPLD) |
| Programmability | — | UV-erase, windowed for lab reprogram |
| Niveau MSL | — | [DATA_NEEDED: MSL rating] |
| Programming Interface | — | JEDEC fuse file via legacy programmer |