EP1810JC-45 vs EP1810JC-25 Comparación
Comparación detallada lado a lado de EP1810JC-45 por Altera y EP1810JC-25 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP1810JC-45 | EP1810JC-25 |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $21,10 | $6,80 |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | Classic EPLD (Erasable Programmable Logic Device) |
| Family | EP1810 (Classic EPLD Family) | Altera/Intel Classic EPLD (EP1810 series) |
| Macrocells | 48 | 48 |
| Equivalent Gates | 2100 gates | — |
| Dedicated Inputs | 12 | 12 |
| I/O Pins | 48 | — |
| Total User I/O | 60 | — |
| Propagation Delay (tpd) | 45 ns | — |
| Frecuencia de reloj máxima | 33.3 MHz | — |
| Technology | CMOS, UV-erasable | CMOS, UV-erasable (windowed ceramic DIP) |
| Maximum Supply Voltage | 5.25 V | — |
| Encapsulado | PLCC-68 (QCCJ, J-Lead, windowed ceramic) | 28-pin ceramic DIP (J) with quartz window |
| Recuento de pines | 68 | — |
| Package Code | QCCJ | — |
| Temperature Grade | Commercial | — |
| Tipo de montaje | Surface Mount | Through-hole |
| Estado RoHS | [DATA_NEEDED: RoHS compliance not stated in verified data] | [DATA_NEEDED: RoHS compliance status] |
| Propagation Delay (tPD) | — | 25 ns |
| Maximum Toggle Frequency | — | [DATA_NEEDED: max fMAX] |
| Input Lines | — | 60 (including I/O) |
| I/O Lines | — | 48 |
| External Clock Inputs | — | 4 |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Temperatura de funcionamiento | — | -40 °C to 85 °C (industrial, per distributor listings) |
| Erasure Method | — | UV light (windowed package) |
| Estado del ciclo de vida | — | NRND (Not Recommended for New Designs) |