EP1810JC-45 vs EP1810JC-25 对比
详细并排对比 EP1810JC-45 出自 Altera 和 EP1810JC-25 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP1810JC-45 | EP1810JC-25 |
|---|---|---|
| 品牌 | Altera | Intel |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 不推荐新设计 | 不推荐新设计 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $21.10 | $6.80 |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | Classic EPLD (Erasable Programmable Logic Device) |
| Family | EP1810 (Classic EPLD Family) | Altera/Intel Classic EPLD (EP1810 series) |
| Macrocells | 48 | 48 |
| Equivalent Gates | 2100 gates | — |
| Dedicated Inputs | 12 | 12 |
| I/O Pins | 48 | — |
| Total User I/O | 60 | — |
| Propagation Delay (tpd) | 45 ns | — |
| 最大时钟频率 | 33.3 MHz | — |
| Technology | CMOS, UV-erasable | CMOS, UV-erasable (windowed ceramic DIP) |
| Maximum Supply Voltage | 5.25 V | — |
| 封装 | PLCC-68 (QCCJ, J-Lead, windowed ceramic) | 28-pin ceramic DIP (J) with quartz window |
| 引脚数量 | 68 | — |
| Package Code | QCCJ | — |
| Temperature Grade | Commercial | — |
| 安装类型 | Surface Mount | Through-hole |
| RoHS 状态 | [DATA_NEEDED: RoHS compliance not stated in verified data] | [DATA_NEEDED: RoHS compliance status] |
| Propagation Delay (tPD) | — | 25 ns |
| Maximum Toggle Frequency | — | [DATA_NEEDED: max fMAX] |
| Input Lines | — | 60 (including I/O) |
| I/O Lines | — | 48 |
| External Clock Inputs | — | 4 |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| 工作温度 | — | -40 °C to 85 °C (industrial, per distributor listings) |
| Erasure Method | — | UV light (windowed package) |
| 生命周期状态 | — | NRND (Not Recommended for New Designs) |