EP1810JC-45 vs EP1810JI-35 Comparación
Comparación detallada lado a lado de EP1810JC-45 por Altera y EP1810JI-35 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP1810JC-45 | EP1810JI-35 |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $21,10 | $18,60 |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | EP1810 (Classic EPLD Family) | — |
| Macrocells | 48 | 48 |
| Equivalent Gates | 2100 gates | — |
| Dedicated Inputs | 12 | 48 |
| I/O Pins | 48 | — |
| Total User I/O | 60 | — |
| Propagation Delay (tpd) | 45 ns | — |
| Frecuencia de reloj máxima | 33.3 MHz | — |
| Technology | CMOS, UV-erasable | — |
| Maximum Supply Voltage | 5.25 V | — |
| Encapsulado | PLCC-68 (QCCJ, J-Lead, windowed ceramic) | 28-pin JLCC (J-leaded ceramic, windowed) |
| Recuento de pines | 68 | — |
| Package Code | QCCJ | — |
| Temperature Grade | Commercial | — |
| Tipo de montaje | Surface Mount | Through-Hole (J-lead) |
| Estado RoHS | [DATA_NEEDED: RoHS compliance not stated in verified data] | [DATA_NEEDED: RoHS compliance for ceramic windowed JLCC] |
| Device Family | — | Classic EPLD |
| Logic Array Blocks | — | 8 LABs of 16 macrocells |
| Pin-to-Pin Propagation Delay (tPD) | — | 35 ns |
| Speed Grade | — | -35 |
| Process Technology | — | CMOS EPROM (UV-erasable) |
| Temperatura de funcionamiento | — | -40C to +85C (Industrial) |
| Tensión de alimentación | — | 5 V (typical classic EPLD) |
| Programmability | — | UV-erase, windowed for lab reprogram |
| Nivel MSL | — | [DATA_NEEDED: MSL rating] |
| Programming Interface | — | JEDEC fuse file via legacy programmer |