EP1810JC-45 vs EP1810JI-35 비교
다음의 상세 나란히 비교: EP1810JC-45 제조: Altera 및 EP1810JI-35 제조: Intel. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EP1810JC-45 | EP1810JI-35 |
|---|---|---|
| 브랜드 | Altera | Intel |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | NRND | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $21.10 | $18.60 |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | EP1810 (Classic EPLD Family) | — |
| Macrocells | 48 | 48 |
| Equivalent Gates | 2100 gates | — |
| Dedicated Inputs | 12 | 48 |
| I/O Pins | 48 | — |
| Total User I/O | 60 | — |
| Propagation Delay (tpd) | 45 ns | — |
| 최대 클록 주파수 | 33.3 MHz | — |
| Technology | CMOS, UV-erasable | — |
| Maximum Supply Voltage | 5.25 V | — |
| 패키지 | PLCC-68 (QCCJ, J-Lead, windowed ceramic) | 28-pin JLCC (J-leaded ceramic, windowed) |
| 핀 수 | 68 | — |
| Package Code | QCCJ | — |
| Temperature Grade | Commercial | — |
| 실장 유형 | Surface Mount | Through-Hole (J-lead) |
| RoHS 상태 | [DATA_NEEDED: RoHS compliance not stated in verified data] | [DATA_NEEDED: RoHS compliance for ceramic windowed JLCC] |
| Device Family | — | Classic EPLD |
| Logic Array Blocks | — | 8 LABs of 16 macrocells |
| Pin-to-Pin Propagation Delay (tPD) | — | 35 ns |
| Speed Grade | — | -35 |
| Process Technology | — | CMOS EPROM (UV-erasable) |
| 동작 온도 | — | -40C to +85C (Industrial) |
| 공급 전압 | — | 5 V (typical classic EPLD) |
| Programmability | — | UV-erase, windowed for lab reprogram |
| MSL 레벨 | — | [DATA_NEEDED: MSL rating] |
| Programming Interface | — | JEDEC fuse file via legacy programmer |