EP1810LC-20 vs EP1810LC-25 Comparación
Comparación detallada lado a lado de EP1810LC-20 por Intel y EP1810LC-25 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP1810LC-20 | EP1810LC-25 |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $7,85 | $8,40 |
| Family | Classic EPLD | — |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Usable Gates | 900 | — |
| Macrocells | 48 | 48 |
| Maximum Operating Frequency | 50 MHz | — |
| Propagation Delay (tPD) | 20 ns | 25 ns |
| Tensión de alimentación | 5 V (4.75 V to 5.25 V) | — |
| Technology | CMOS EPROM | CMOS EPLD (erasable programmable logic device) |
| Programmability | UV-Erasable / OTP | — |
| Dedicated Inputs | 12 | 12 |
| Encapsulado | 68-pin PLCC | 68-pin JLCC (J-leaded ceramic chip carrier) |
| Package Suffix | LC (PLCC, windowed for UV erase on L variant) | — |
| Speed Grade | 20 ns (commercial) | — |
| Temperatura de funcionamiento | 0C to +70C (commercial) | [DATA_NEEDED: temperature grade for LC package] |
| Tipo de montaje | Surface Mount | Surface Mount |
| Estado RoHS | [DATA_NEEDED: rohs status] | [DATA_NEEDED: RoHS compliance not confirmed in legacy datasheet] |
| Product Family | — | Altera Classic EPLD |
| Part Number | — | EP1810LC-25 |
| I/O Pins | — | 48 |
| External Clock Inputs | — | 4 |
| Supply Voltage (VCC) | — | 5 V (TTL-compatible) |
| Operating Mode | — | Turbo-only (no slow-power mode) |
| Package Code | — | LC = 68-pin JLCC |
| Programmable Interconnect | — | Global + Local buses |
| Programming Method | — | Altera Classic programmer + MAX+PLUS II legacy flow |
| Estado del ciclo de vida | — | Obsolete (legacy Altera Classic family) |