EP1810LC-35 vs EP1810JC-35 Comparación
Comparación detallada lado a lado de EP1810LC-35 por Rochester Electronics y EP1810JC-35 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Rochester Electronics
EP1810LC-35 - 48-Macrocell Classic EPLD, 35ns, PLCC-68 | Rochester/Altera
EP1810LC-35 ⚠ Última compra
Comparación de especificaciones
| Parámetro | EP1810LC-35 | EP1810JC-35 |
|---|---|---|
| Marca | Rochester Electronics | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Última compra | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $49,20 | $5,48 |
| Device Type | EPLD (Erasable Programmable Logic Device) | UV-Erasable Complex PLD (UV PLD / CPLD) |
| Series | Classic EP1810 | — |
| Macrocells | 48 | — |
| Equivalent Gates | 900 usable / 2100 equivalent | — |
| Maximum Operating Frequency | 28.6 MHz | — |
| Propagation Delay (tpd) | 35 ns (max, '-35' speed grade) | 35 ns (max) |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | — |
| Technology | CMOS, UV-erasable EPROM | — |
| Encapsulado | 68-pin PLCC (J-Lead) | — |
| Tipo de montaje | Surface Mount (socketable) | Surface Mount (J-Lead) |
| Temperatura de funcionamiento | 0C to +70C (commercial) | — |
| I/O Pins | [DATA_NEEDED: I/O count exact] | — |
| Configuration Method | UV-erase + EPROM programmer | — |
| Programmable Interconnect | Centralized Programmable Interconnect Array (PIA) | — |
| Development Tool (legacy) | MAX+PLUS II / A+PLUS | — |
| Estado RoHS | [DATA_NEEDED] | Compliant (per Altera listing) |
| Lead-Free | [DATA_NEEDED] | — |
| Device Family | — | Classic EPLD (EP1810) |
| Number of Macrocells | — | 48 |
| Frecuencia de reloj máxima | — | [DATA_NEEDED: fmax for this speed grade] |
| Process Technology | — | CMOS |
| Supply Voltage (Vcc) | — | 5 V (nominal) |
| Maximum Supply Voltage | — | 5.25 V (per distributor listing) |
| Package Type | — | CQCC-68 (Ceramic J-Lead Chip Carrier, QCCJ) |
| Number of Terminals | — | 68 |
| Terminal Form | — | J-Bend |
| Rango de temperatura de funcionamiento | — | 0°C to 70°C (Commercial) |
| Temperature Grade | — | Commercial |
| Erasure Method | — | UV (quartz-windowed ceramic package) |
| Lead-Free Status | — | Lead-free (per distributor listing) |
| Logic Architecture | — | Programmable AND/OR array with macrocell outputs |