EP1810LC-35 vs EP1810LC-45 Comparación
Comparación detallada lado a lado de EP1810LC-35 por Rochester Electronics y EP1810LC-45 por Rochester Electronics. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Rochester Electronics
EP1810LC-35 - 48-Macrocell Classic EPLD, 35ns, PLCC-68 | Rochester/Altera
EP1810LC-35 ⚠ Última compraRochester Electronics
EP1810LC-45 - 900-Gate Classic EPLD, 48 Macro Cells, PLCC-68 | Intel
EP1810LC-45 ObsoleteComparación de especificaciones
| Parámetro | EP1810LC-35 | EP1810LC-45 |
|---|---|---|
| Marca | Rochester Electronics | Rochester Electronics |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Última compra | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $49,20 | $49,90 |
| Device Type | EPLD (Erasable Programmable Logic Device) | EPLD (Erasable Programmable Logic Device) |
| Series | Classic EP1810 | — |
| Macrocells | 48 | — |
| Equivalent Gates | 900 usable / 2100 equivalent | — |
| Maximum Operating Frequency | 28.6 MHz | 22.2 MHz |
| Propagation Delay (tpd) | 35 ns (max, '-35' speed grade) | 45 ns |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | — |
| Technology | CMOS, UV-erasable EPROM | — |
| Encapsulado | 68-pin PLCC (J-Lead) | 68-pin PLCC (J-lead) |
| Tipo de montaje | Surface Mount (socketable) | Surface Mount (PLCC socket compatible) |
| Temperatura de funcionamiento | 0C to +70C (commercial) | 0 °C to +70 °C (commercial) |
| I/O Pins | [DATA_NEEDED: I/O count exact] | — |
| Configuration Method | UV-erase + EPROM programmer | — |
| Programmable Interconnect | Centralized Programmable Interconnect Array (PIA) | — |
| Development Tool (legacy) | MAX+PLUS II / A+PLUS | — |
| Estado RoHS | [DATA_NEEDED] | [DATA_NEEDED: RoHS status of Rochester-sourced part] |
| Lead-Free | [DATA_NEEDED] | [DATA_NEEDED: lead-free finish] |
| Family | — | Altera Classic EPLD |
| Usable Gates | — | 900 |
| Macro Cells | — | 48 |
| Maximum Inputs | — | 64 |
| Maximum Outputs | — | 48 |
| Logic Array Blocks | — | 4 |
| Supply Voltage (Vcc) | — | 5 V (±5%) |
| Process Technology | — | 5 V CMOS EPROM |