EP1810LC-35 vs EP1810LI-25 Comparación
Comparación detallada lado a lado de EP1810LC-35 por Rochester Electronics y EP1810LI-25 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Rochester Electronics
EP1810LC-35 - 48-Macrocell Classic EPLD, 35ns, PLCC-68 | Rochester/Altera
EP1810LC-35 ⚠ Última compraComparación de especificaciones
| Parámetro | EP1810LC-35 | EP1810LI-25 |
|---|---|---|
| Marca | Rochester Electronics | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Última compra | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $49,20 | $9,95 |
| Device Type | EPLD (Erasable Programmable Logic Device) | EPLD (Erasable Programmable Logic Device), UV-erasable / OTP |
| Series | Classic EP1810 | — |
| Macrocells | 48 | 48 |
| Equivalent Gates | 900 usable / 2100 equivalent | — |
| Maximum Operating Frequency | 28.6 MHz | — |
| Propagation Delay (tpd) | 35 ns (max, '-35' speed grade) | — |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | 4.5 V to 5.5 V (nominal 5 V) |
| Technology | CMOS, UV-erasable EPROM | — |
| Encapsulado | 68-pin PLCC (J-Lead) | 68-pin PLCC (J68, J-Lead) |
| Tipo de montaje | Surface Mount (socketable) | — |
| Temperatura de funcionamiento | 0C to +70C (commercial) | — |
| I/O Pins | [DATA_NEEDED: I/O count exact] | 48 |
| Configuration Method | UV-erase + EPROM programmer | — |
| Programmable Interconnect | Centralized Programmable Interconnect Array (PIA) | — |
| Development Tool (legacy) | MAX+PLUS II / A+PLUS | — |
| Estado RoHS | [DATA_NEEDED] | unknown |
| Lead-Free | [DATA_NEEDED] | — |
| Family | — | Altera Classic EPLD |
| Usable Gates | — | 900 |
| Propagation Delay (tPD) | — | 25 ns |
| Maximum Counter Frequency | — | 40 MHz |
| Dedicated Inputs | — | 12 |
| Global Clock Inputs | — | 4 |
| Interconnect | — | Programmable global and local buses |
| JESD-30 Package Code | — | S-PQCC-J68 |
| Process Technology | — | CMOS |
| Operating Temperature (Industrial 'I' suffix) | — | -40 C to +85 C |
| Programming Mode | — | EPROM/UV-erasable (windowed) and OTP |
| Development Tool | — | Altera MAX+PLUS II |
| Lead-Free Status | — | unknown |