EP1810LC-35T vs EP1810LC-20 Comparación
Comparación detallada lado a lado de EP1810LC-35T por Intel y EP1810LC-20 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP1810LC-35T | EP1810LC-20 |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $115,20 | $7,85 |
| Device Family | EP1810 Classic EPLD | — |
| Product Type | Erasable Programmable Logic Device (EPLD) | — |
| Usable Gates | 900 | 900 |
| Macro Cells | 48 | — |
| Pin-to-Pin Delay (tpd) | 35 ns | — |
| Maximum Frequency (fmax) | 28.6 MHz | — |
| Supply Voltage (Vcc) | 5 V | — |
| Technology | CMOS | CMOS EPROM |
| Logic Compatibility | 100% TTL emulation | — |
| Encapsulado | 68-pin PLCC (Plastic Leaded Chip Carrier) | 68-pin PLCC |
| Package Suffix | T = Tape and Reel | LC (PLCC, windowed for UV erase on L variant) |
| Temperatura de funcionamiento | 0 C to +70 C (Commercial) | 0C to +70C (commercial) |
| Tipo de montaje | Surface Mount (PLCC socket or direct solder) | Surface Mount |
| Programming Method | UV-erasable (ceramic) / OTP (plastic); MAX+PLUS II | — |
| Estado RoHS | Non-compliant (legacy PLCC product) | [DATA_NEEDED: rohs status] |
| Logic Family Replacement Target | 74LS low-power Schottky TTL | — |
| Family | — | Classic EPLD |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Macrocells | — | 48 |
| Maximum Operating Frequency | — | 50 MHz |
| Propagation Delay (tPD) | — | 20 ns |
| Tensión de alimentación | — | 5 V (4.75 V to 5.25 V) |
| Programmability | — | UV-Erasable / OTP |
| Dedicated Inputs | — | 12 |
| Speed Grade | — | 20 ns (commercial) |