EP1810LC-35T vs EP1810LC-30 Comparación
Comparación detallada lado a lado de EP1810LC-35T por Intel y EP1810LC-30 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP1810LC-35T | EP1810LC-30 |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $115,20 | $9,95 |
| Device Family | EP1810 Classic EPLD | — |
| Product Type | Erasable Programmable Logic Device (EPLD) | Classic EPLD (Erasable Programmable Logic Device) |
| Usable Gates | 900 | — |
| Macro Cells | 48 | — |
| Pin-to-Pin Delay (tpd) | 35 ns | — |
| Maximum Frequency (fmax) | 28.6 MHz | — |
| Supply Voltage (Vcc) | 5 V | — |
| Technology | CMOS | CMOS, low-power (LC) |
| Logic Compatibility | 100% TTL emulation | — |
| Encapsulado | 68-pin PLCC (Plastic Leaded Chip Carrier) | JLCC-68 (68-pin J-Lead ceramic chip carrier) |
| Package Suffix | T = Tape and Reel | — |
| Temperatura de funcionamiento | 0 C to +70 C (Commercial) | [DATA_NEEDED: temperature grade] |
| Tipo de montaje | Surface Mount (PLCC socket or direct solder) | — |
| Programming Method | UV-erasable (ceramic) / OTP (plastic); MAX+PLUS II | — |
| Estado RoHS | Non-compliant (legacy PLCC product) | unknown (legacy ceramic package) |
| Logic Family Replacement Target | 74LS low-power Schottky TTL | — |
| Family | — | Altera Classic EPLD |
| Macrocells | — | 48 |
| Flip-Flops | — | 48 (one per macrocell) |
| Speed Grade (tPD) | — | 30 ns |
| Tensión de alimentación | — | 5 V (typical) |
| Programming | — | Device programmer or JTAG |
| Standby Current | — | [DATA_NEEDED: ICC standby] |
| Número de pines | — | 68 |
| Number of I/O Pins | — | [DATA_NEEDED: I/O count] |
| Logic Blocks | — | 48 macrocells |