EP1810LC-35T vs EP1810LC-30 비교
다음의 상세 나란히 비교: EP1810LC-35T 제조: Intel 및 EP1810LC-30 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EP1810LC-35T | EP1810LC-30 |
|---|---|---|
| 브랜드 | Intel | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $115.20 | $9.95 |
| Device Family | EP1810 Classic EPLD | — |
| Product Type | Erasable Programmable Logic Device (EPLD) | Classic EPLD (Erasable Programmable Logic Device) |
| Usable Gates | 900 | — |
| Macro Cells | 48 | — |
| Pin-to-Pin Delay (tpd) | 35 ns | — |
| Maximum Frequency (fmax) | 28.6 MHz | — |
| Supply Voltage (Vcc) | 5 V | — |
| Technology | CMOS | CMOS, low-power (LC) |
| Logic Compatibility | 100% TTL emulation | — |
| 패키지 | 68-pin PLCC (Plastic Leaded Chip Carrier) | JLCC-68 (68-pin J-Lead ceramic chip carrier) |
| Package Suffix | T = Tape and Reel | — |
| 동작 온도 | 0 C to +70 C (Commercial) | [DATA_NEEDED: temperature grade] |
| 실장 유형 | Surface Mount (PLCC socket or direct solder) | — |
| Programming Method | UV-erasable (ceramic) / OTP (plastic); MAX+PLUS II | — |
| RoHS 상태 | Non-compliant (legacy PLCC product) | unknown (legacy ceramic package) |
| Logic Family Replacement Target | 74LS low-power Schottky TTL | — |
| Family | — | Altera Classic EPLD |
| Macrocells | — | 48 |
| Flip-Flops | — | 48 (one per macrocell) |
| Speed Grade (tPD) | — | 30 ns |
| 공급 전압 | — | 5 V (typical) |
| Programming | — | Device programmer or JTAG |
| Standby Current | — | [DATA_NEEDED: ICC standby] |
| 핀 수 | — | 68 |
| Number of I/O Pins | — | [DATA_NEEDED: I/O count] |
| Logic Blocks | — | 48 macrocells |